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Explorer
Explorer
11,125 Views
Registered: ‎03-10-2015

why am I getting these warning

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Hello,

 

   I am getting the 

 

WARNING: [Synth 8-3331] design system_stub has unconnected port FCLK_RESET1_N
WARNING: [Synth 8-3331] design system_stub has unconnected port FCLK_CLK1

 

but looking at the code it is driven from the system as shown below;

 

entity system_stub is

port (

    FCLK_RESET1_N : out std_logic;
    FCLK_CLK1 : out std_logic;

     ...

);
end system_stub;

 

architecture STRUCTURE of system_stub is

component system is
port (

FCLK_RESET1_N : out std_logic;

FCLK_CLK1 : out std_logic;

...

);

end component;

 

begin

 

system_i : system
port map (

FCLK_CLK1 => PCLK100MHZ,

FCLK_RESET1_N => PROC_SYSRSTL,

);

 

Can anyone to please let me know why am I getting the warning?

 

Best Regards,

Fred

 

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1 Solution

Accepted Solutions
Moderator
Moderator
16,702 Views
Registered: ‎07-21-2014

Re: why am I getting these warning

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Hi,

 

Refer below discussion:

http://forums.xilinx.com/t5/New-Users-Forum/VHDL-Beginner-Not-able-to-solve-port-mapping-error-Cannot-read/m-p/440334/highlight/true#M9356

 

Thanks,
Anusheel
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12 Replies
Xilinx Employee
Xilinx Employee
11,118 Views
Registered: ‎09-20-2012

Re: why am I getting these warning

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Hi,

Can you show us complete instantiation of system module?

In the system_i instantiation in the rhs part you need to have these port names FCLK_CLK1 etc.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Moderator
Moderator
11,104 Views
Registered: ‎07-21-2014

Re: why am I getting these warning

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Hi,

 

There is no connection for below ports:

entity system_stub is

port (

    FCLK_RESET1_N : out std_logic;
    FCLK_CLK1 : out std_logic;

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
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Explorer
Explorer
11,088 Views
Registered: ‎03-10-2015

Re: why am I getting these warning

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Hi Deepika,

 

  where is this rhs located? do you want the system.bd file?

 

Regards, Fred

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Xilinx Employee
Xilinx Employee
11,083 Views
Registered: ‎09-20-2012

Re: why am I getting these warning

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Hi,

 

Just attach the top level wrapper file where you have instantiation of system_i module.

 

If this is block design wrapper file just remove this file and create the wrapper file again. See if this helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Explorer
Explorer
10,787 Views
Registered: ‎03-10-2015

Re: why am I getting these warning

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Hi Deepika,

 

  Here is the wrapper...

 

Regards, Fred

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Xilinx Employee
Xilinx Employee
10,782 Views
Registered: ‎09-20-2012

Re: why am I getting these warning

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Hi,

 

It looks like you have edited the wrapper file. I see that you have not connected the FCLK_RESET1_N and FCLK_CLK1 ports in the design. You have defined them as output ports for system_stub module but no where assigned them.

 

If you want to connect these ports to submodule output pins then you need to write them in right hand side of the instantiation as below

 

submodule_output_port1 => FCLK_RESET1_N,

submodule_output_port2 => FCLK_CLK1,

 

Thanks,

Deepika.

 

 

Thanks,
Deepika.
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Explorer
Explorer
10,755 Views
Registered: ‎03-10-2015

Re: why am I getting these warning

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Hi,

 

  I am doing what you suggested (as shown in the code) but still getting the warning...

 

Regards, Fred

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Xilinx Employee
Xilinx Employee
10,737 Views
Registered: ‎09-20-2012

Re: why am I getting these warning

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Hi Fred,

Can you attach the modified wrapper file?

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Explorer
Explorer
10,721 Views
Registered: ‎03-10-2015

Re: why am I getting these warning

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i did but here it goes again...

 

Fred

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Xilinx Employee
Xilinx Employee
8,183 Views
Registered: ‎09-20-2012

Re: why am I getting these warning

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Hi,

 

Read my earlier post again. I said that you need to have FCLK_RESET1_N on the right hand side where as you have some other signal on line 573.

 

FCLK_RESET1_N => PROC_SYSRSTL,

 

Thanks,

Deepika.

Thanks,
Deepika.
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Explorer
Explorer
8,129 Views
Registered: ‎03-10-2015

Re: why am I getting these warning

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Hi Deepika,

 

  I did what you suggested now the tool complain that 

[Synth 8-1779] cannot read from 'out' object fclk_reset1_n ; use 'buffer' or 'inout' ...

[Synth 8-1779] cannot read from 'out' object fclk_clk1 ; use 'buffer' or 'inout' ...

 

I don't want to mark as buffer or inout LOL

 

Regards, Fred

 

 

 

 

 

 

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Moderator
Moderator
16,703 Views
Registered: ‎07-21-2014

Re: why am I getting these warning

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Hi,

 

Refer below discussion:

http://forums.xilinx.com/t5/New-Users-Forum/VHDL-Beginner-Not-able-to-solve-port-mapping-error-Cannot-read/m-p/440334/highlight/true#M9356

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

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