12-31-2020 11:36 AM
I design a simple axi4 ip but fail at 2nd write in simulation.
It's in Vvivado 2018.3 and windows 10.
To simple, the user logic only
In my old axi4 ip, the simulation is normal.
The bench test are:
Write 1,2,3,4 at addr 0, then 24 at 4, 48 at 8, 58 at 12, each write follows a read.
It works well, maybe in 2015.4 or 2018.2. number of registers is 4
In 2018.3 , the custom axi4 ip's number of registers is 16, I use almost same bench test program, but the simulation block at 2nd write. It wait awready and wready to be 1.
I find it has a aw_en signal more, I also add a flag for indicate write begin and end.
I attach ipa,zip ( the normal one which made in 2018.2 or 2015.4 version;
ip2.zip which made in 2018.3 and block at 2nd write.
Any advice is appreciate. I also hope to know the aw_en meaning.
12-31-2020 01:31 PM - edited 12-31-2020 02:05 PM
I find that it is blocked by aw_en.
if aw_en =1, it will be ok.
// Implement axi_awready generation // axi_awready is asserted for one S_AXI_ACLK clock cycle when both // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is // de-asserted when reset is low. always @( posedge S_AXI_ACLK ) begin if ( S_AXI_ARESETN == 1'b0 ) begin axi_awready <= 1'b0; aw_en <= 1'b1; end else begin if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) begin // slave is ready to accept write address when // there is a valid write address and write data // on the write address and data bus. This design // expects no outstanding transactions. axi_awready <= 1'b1; aw_en <= 1'b0; end else if (S_AXI_BREADY && axi_bvalid) begin aw_en <= 1'b1; axi_awready <= 1'b0; end else begin axi_awready <= 1'b0; aw_en <= 1'b1; //code added in 2020/12/31 end end end
aw_en =1 should be else if (S_AXI_BREADY && axi_bvalid)
but axi_bvalid is 0, aw_en can't be 1,
I add a line code in else (aw_en=1)
Now I could all the write as follows:
Maybe the else if should be:
else if (S_AXI_BREADY && ~axi_bvalid)
I'm not sure the change as I change the official code. Maybe I should ask xilinx.
Then I chek the ila wave, axi_bvalid should be 1. I made something wrong.
Where is the wrong?
01-01-2021 07:00 AM
The problem you are having is due to a race condition (or two or three) in your test bench. The AXI signals generated by your master should be synchronous with the clock. In the test bench design you've shared, they are not. The resulting race condition(s) don't how up in your trace.
The attached test bench makes the AXI master inputs synchronous, resets the AXI master signals with the reset, fixes the other race condition between AWREADY and WREADY, and as a result has no problems. (The race condition on AWREADY and WREADY wasn't the problem, but in general you can't rely upon these two signals being valid at the same time. A slave might accept AWVALID before WVALID, or vice versa, or accept both on the same clock as the case is with this slave.)
The test bench I'm returning still has in the read side--I just updated the write half. The read half should also be made synchronous.
You should also be aware that Xilinx's AXI demo's are horribly broken. Since the revealing the bugs in their AXI-lite slave demo they fixed the write side (and dropped it's throughput from 50% to 33%), but the read half of the design remains broken. Your simulation, as written, will not reveal the bugs although certain configurations of MicroBlaze and the interconnect have been known to trigger them.
I think you'll find this slave example easier to work with. Even better, it doesn't violate protocol.
01-01-2021 07:23 AM
Just as another note, you can see problems in your first trace long before the second write where you noticed the failure.
01-01-2021 09:27 PM - edited 01-01-2021 09:41 PM
Thanks for your response!
I think that i need got axi_bvalid been 1.
I check the condition:
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
and think that I maybe need to last more time for awready, wready.
So I change the axi_awready and axi_wready cycle:
axi_wready <= 1'b0;
Then the simulation seems right.
I also change the bench.v file ,let write finish wait axi_bvalid signal.
Is my change acceptable?
I also don't understand that aw_en changes before bvalid.
01-02-2021 08:09 AM
Looks like you broke things worse in that last screen shot.
If you want to share this updated design, I'll take a peek at it to check for protocol compliance.