cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
561 Views
Registered: ‎05-21-2019

write_bitstream ERROR

Hi,

I've been working on the Xilinx DPD IP v9.0. I'm having the following error when I try and generate the bit-stream for the IP core. I'm able to synthesize and implement the design successfully. However, when it comes to Generating Bitstream, I encounter the following error. Kindly help me with this. 

 

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
zynq_1_i/RFISS0/RFIF_1/jesd204_tx_0/inst/i_zynq_1_jesd204_tx_0_0 (<encrypted cellview>)
zynq_1_i/RFISS0/RFIF_1/jesd204_rx_0/inst/i_zynq_1_jesd204_rx_0_0 (<encrypted cellview>)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

I've tried resetting and regenerating the IP output products but all in vain.

Regards,

B.Varsha

0 Kudos
7 Replies
Highlighted
Xilinx Employee
Xilinx Employee
525 Views
Registered: ‎07-16-2008

Do you have hardware evaluation or full license for this IP?

You can do a quick check by selecting the IP from IP Catalog, and run "license status" from right-click menu.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
508 Views
Registered: ‎05-21-2019

Hi,

I've an Hardware Evaluation License. Verified through the quick check you had mentioned.

Regards,

B.Varsha

licence_status_dpd.png
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
499 Views
Registered: ‎07-16-2008

What about the IP JESD204, which the error is complaining about?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
495 Views
Registered: ‎05-21-2019

Hi,

The Licence Status for JESD204 happens to be Design_Linking. 

licence_status_jesd204.png
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
493 Views
Registered: ‎07-16-2008

So that's the problem. 'Design Linking' means simulation only. It doesn't enable bitstream generation of the JESD204 IP.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
486 Views
Registered: ‎05-21-2019

Hi,

Okay, but I require the hardware description file of this design for generating the Petalinux Image for Linux. Hence, I need to generate the bitstream and include it. Is there a way out? 

Thanks and Regards,

B.Varsha

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
484 Views
Registered: ‎07-16-2008

You'll have to have a valid IP license to proceed bitstream generation.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos