06-11-2019 02:01 AM
I've been working on the Xilinx DPD IP v9.0. I'm having the following error when I try and generate the bit-stream for the IP core. I'm able to synthesize and implement the design successfully. However, when it comes to Generating Bitstream, I encounter the following error. Kindly help me with this.
[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
zynq_1_i/RFISS0/RFIF_1/jesd204_tx_0/inst/i_zynq_1_jesd204_tx_0_0 (<encrypted cellview>)
zynq_1_i/RFISS0/RFIF_1/jesd204_rx_0/inst/i_zynq_1_jesd204_rx_0_0 (<encrypted cellview>)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
I've tried resetting and regenerating the IP output products but all in vain.
06-12-2019 06:38 PM - edited 06-12-2019 06:39 PM
Do you have hardware evaluation or full license for this IP?
You can do a quick check by selecting the IP from IP Catalog, and run "license status" from right-click menu.
06-12-2019 10:48 PM
What about the IP JESD204, which the error is complaining about?
06-12-2019 10:57 PM
So that's the problem. 'Design Linking' means simulation only. It doesn't enable bitstream generation of the JESD204 IP.
06-12-2019 11:01 PM
Okay, but I require the hardware description file of this design for generating the Petalinux Image for Linux. Hence, I need to generate the bitstream and include it. Is there a way out?
Thanks and Regards,
06-12-2019 11:03 PM
You'll have to have a valid IP license to proceed bitstream generation.