09-30-2015 05:41 PM
I have an ip core i've generated using the 7 series transceiver wizard. When I go through the wizard I specify 125 MHz as my reference clock frequency. However, when I run the core in hardware I see 156.25 MHz at the txoutclk. I've verified that my input clock is 125 MHz. I have this going through a buffer and then to gtrefclk0_in.
Why is the ip core I've generated changing the txout clk to 156.25 when it should be 125 MHz?
09-30-2015 06:03 PM
What is the source of your TXOUTCLK? See page 150 of UG476: there are several sources and different dividers available for TXOUTCLK.
10-01-2015 08:03 AM
hmm, not sure I have control over that. When I use the wizard I spec a frequency of 125 MHz and a line rate of 3.125 GHz and it generates a bunch of files. The wrapper I've written to instantiate the <name>_GT module doesn't have any controllable parameters for the pll.
Is the tx_clk output always fixed at 156.25 MHz for some reason?
10-01-2015 10:10 AM
No, it is not always that frequency, but depending on the external and internal data widths along with the line rate, it might be a preferable frequency.
Look at the "Encoding and Clocking" tab of the GT Wizard.
10-01-2015 10:18 AM
oh, I think I get it now. Looking at the 7 series gtx transceiver guide Equation 3-1 the txusrclk rate is just the line rate over the internal data width. So, with a line rate of 3.125 GHz and a data width of 20 I should get 156.25 MHz, which I see on my scope. So, the txusrclk just depends on those two numbers and not on the input frequency. The wizard sets up pll based on input clk, line rate and data width. Does that all sound correct?