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Registered: ‎11-26-2018

xci in project file

I am using Vivado 2018.2 on a windows10 to compile a Kintex 7 device.  From the gui, I searched and added the .xci for the cores that I had generated.  when elaborate the design (from the gui), I get multiple warnings similar to this:

  • [Project 1-863] The design checkpoint file ..../cores/managed_ip_project/managed_ip_project.runs/afifo_fwft_bram_96x16_synth_1/afifo_fwft_bram_96x16.dcp was generated for a block design or an IP or BD by an out of context synthesis run and should not directly be used as a source in a Vivado flow to refer to an IP source. As of 2017.1, the DCP from OOC runs will not contain XDC timing constraints because these are expected to be referred to by the IP .xci or .xcix file source. DCP files prior to 2017.1 will contain incorrect constraints because they were generated with default OOC clock period which will not likely match your top level clock constraints when used in the full design context.

The first time these error sshowed up, I had pulled in the VHD file for the various cores, so i deleted the souce  link to all the cores and then went and referecned the .xci file.  How do I get rid of these warngings?

Also, when I look in the project direcotry, I see many files referred to (.xcd, .cdp. .v, .vhd, .xdc, etc.), but when I look in the IP sources list ( in the gui), the .xci file does not show up anywhere.  What is the miniumum file set that needs to be reffered to int the project directory?

This is kind of stopping me from moving forward until I can resolve the warnings.


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Registered: ‎07-16-2008

This warning is typically seen when you add IP DCP files as source file to project. We recommend IP is added to project in the form of .xci so the IP files can be correctly managed.

The following AR talks about this change.


However, from your description it's unclear why .xci is not displayed in IP sources view. Can you attach the project archive for a look?


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