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Explorer
Explorer
720 Views
Registered: ‎11-01-2015

A question about PR used in UltraScale

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Hi, 

 

It is said that the height of a Pblock for a RP must be a clock region, so if the height is two or more clock regions, is it be supported?

 

Thanks,

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Xilinx Employee
Xilinx Employee
656 Views
Registered: ‎11-17-2008

Re: A question about PR used in UltraScale

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@araongao2015,

 

In UltraScale and UltraScale+, you can draw any shape you'd like and Vivado will automatically snap to legal boundaries. When creating pblocks in the Vivado IDE, take a look at the shading -- this indicates the resources that have been selected for the Reconfigurable Partition.  Use the hd_visual scripts to explicitly view the tiles identified for placement and routing (they'll be different) for your RP -- see UG909 for more info here.

 

The granularity of the bitstream will align vertically with clock regions, but you do not have to manually align the pblocks to this edge, as Hong notes.  In fact, if you leave the height just short of the clock region boundary, Vivado will use that gap for just RM routing, but keep it free for static logic placement (and routing).  And yes, an RP can be multiple clock regions high, even as high as the full device, including for SSI devices.

 

thanks,

david.

2 Replies
Moderator
Moderator
713 Views
Registered: ‎11-04-2010

Re: A question about PR used in UltraScale

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Hi, @araongao2015 ,
It's suggested to have the height of a Pblock for a RP to be aligned with the height of clock region.  Not MUST.
Yes, you can make a pblock for a RP with height of two or more clock regions.

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Xilinx Employee
Xilinx Employee
657 Views
Registered: ‎11-17-2008

Re: A question about PR used in UltraScale

Jump to solution

@araongao2015,

 

In UltraScale and UltraScale+, you can draw any shape you'd like and Vivado will automatically snap to legal boundaries. When creating pblocks in the Vivado IDE, take a look at the shading -- this indicates the resources that have been selected for the Reconfigurable Partition.  Use the hd_visual scripts to explicitly view the tiles identified for placement and routing (they'll be different) for your RP -- see UG909 for more info here.

 

The granularity of the bitstream will align vertically with clock regions, but you do not have to manually align the pblocks to this edge, as Hong notes.  In fact, if you leave the height just short of the clock region boundary, Vivado will use that gap for just RM routing, but keep it free for static logic placement (and routing).  And yes, an RP can be multiple clock regions high, even as high as the full device, including for SSI devices.

 

thanks,

david.