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Adventurer
Adventurer
8,879 Views
Registered: ‎06-25-2015

Best way to divide a clock by two

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Hello,

 

I am wondering which would be the best approach of dividing a clock signal by two. 

 

The first approach would be to use an always statement

 

always @(posedge clk) 

        new_clk <= ~new_clk

 

The second approach would be to use the mmcm or pll.

 

I am using the system clock (200 MHz) of the KC705 and need a 100 MHz clock to drive the DRP for the MGT.

 

Thank you for your time

 

Adam Gropp 

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1 Solution

Accepted Solutions
Historian
Historian
15,386 Views
Registered: ‎01-23-2009

Re: Best way to divide a clock by two

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In regards to constraining the output of the BUFGCE, should I use create_clock and specify the period and duty cycle.

 

You should use create_generated_clock. Assume the BUFGCE instance name is my_bufgce

 

create_generated_clock -name clk_div2 -divide_by 2 -duty_cycle 25 -source [get_pins my_bufgce/I] [get_pins my_bufgce/O]

 

or (more precisely, but a little less clear)

 

create_generated_clock -name clk_div2 -edges {1 2 5}  -source [get_pins my_bufgce/I] [get_pins my_bufgce/O]

 

Avrum

14 Replies
Xilinx Employee
Xilinx Employee
8,882 Views
Registered: ‎08-02-2011

Re: Best way to divide a clock by two

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Hi Adam,

 

You should never divide a clock using logic like that (and then use it as an actual clock) because it will force the clock on to general purpose routing and thus have very high skew and be difficult to meet timing.

 

Instead, you could indeed use a MMCM/PLL if you have them to spare, but they're usually precious commodities.

 

Another option is to divide it using the always block like shown but use 'new_clk' as a clock enable instead of an actual clock.

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Historian
Historian
8,862 Views
Registered: ‎01-23-2009

Re: Best way to divide a clock by two

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I agree with all the suggestions given by @bwiec (although I don't think you can use the 200MHz with a CE for the DRP),   but want to add one more - the use of the BUFGCE or BUFHCE to generate the "divided" clock (it's not really divided, since it ends up with a 25% duty cycle but for most applications this is acceptable). Take a look at this post on using a BUFGCE/BUFHCE.

 

Avrum

 

 

Adventurer
Adventurer
8,828 Views
Registered: ‎06-25-2015

Re: Best way to divide a clock by two

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Hello @bwiec,

 

Thank you for your insight. To check my understanding of using clock enable is this what you mean,

 

reg clk_en_r;

wire clk_en;

 

always@(posedge clk)

    clk_en_r <= ~clk_en_r;

 

assign clk_en = clk_en_r;

 

always @(posedge clk) begin

    if (clk_en) begin

       ...other stuff

 

Also, I have been curious about a recommended way of handling this. Should I assign clk_en_r to a wire and use the wire to check as I have done or is there no real advantage. I believe that it will work either way. 

 

Anyway, I do believe that I will use @avrumw suggestion of BUFGCE since the DRP operates on the rising edge of drpclk and the 25% duty cycle does not seem to be a problem.

 

In regards to constraining the output of the BUFGCE, should I use create_clock and specify the period and duty cycle. I do not have a good understanding of when signals need to be constrained and when not to.

 

Thank both of you for you information and time.

 

Adam Gropp

 

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Xilinx Employee
Xilinx Employee
8,829 Views
Registered: ‎08-02-2011

Re: Best way to divide a clock by two

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Thank you for your insight. To check my understanding of using clock enable is this what you mean,
 
reg clk_en_r;
wire clk_en;
 
always@(posedge clk)
    clk_en_r <= ~clk_en_r;
 
assign clk_en = clk_en_r;
 
always @(posedge clk) begin
    if (clk_en) begin
       ...other stuff

Yes, exactly!

 

Also, I have been curious about a recommended way of handling this. Should I assign clk_en_r to a
wire and use the wire to check as I have done or is there no real advantage. I believe that it will
work either way.

The only time I personally do something like that is to assign output wires (because I think having a mix of initialized reg's and default wire types in the port list is ugly, but it's just personal preference). In this case, there's no advantage that I can think of for assigning it to a wire... you could use it directly:

 

always @ (posedge clk)
  if (clk_en_r)
    ... other stuff

 

www.xilinx.com
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Historian
Historian
15,387 Views
Registered: ‎01-23-2009

Re: Best way to divide a clock by two

Jump to solution

In regards to constraining the output of the BUFGCE, should I use create_clock and specify the period and duty cycle.

 

You should use create_generated_clock. Assume the BUFGCE instance name is my_bufgce

 

create_generated_clock -name clk_div2 -divide_by 2 -duty_cycle 25 -source [get_pins my_bufgce/I] [get_pins my_bufgce/O]

 

or (more precisely, but a little less clear)

 

create_generated_clock -name clk_div2 -edges {1 2 5}  -source [get_pins my_bufgce/I] [get_pins my_bufgce/O]

 

Avrum

Adventurer
Adventurer
8,818 Views
Registered: ‎06-25-2015

Re: Best way to divide a clock by two

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@avrumw Thank you very much for this. One more question regarding this constraint. It could be trivial but -name spot, is this the name of the signal for instance

 

BUFGCE drp_bufgce(
.I(drpclk_in),
.O(drpclk_in_i),
.CE(drpclk_en)
);

 

create_generated_clock -name drpclk_in_i -divide_by 2 -duty_cycle 25 -source [get_pins my_drp_bufgce/I] [get_pins drp_bufgce/O]

 

Thank you for your time

 

Adam

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Historian
Historian
8,817 Views
Registered: ‎01-23-2009

Re: Best way to divide a clock by two

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The -name is the name given to the clock you are creating - it can be anything you want.

 

Since the source and clock attachment points are both pins (specified with the get_pins command) they should use the instance name of the BUFGCE

 

create_generated_clock -name xxyyzz -divide_by 2 -duty_cycle 25 -source [get_pins drp_bufgce/I] [get_pins drp_bufgce/O]

 

(there was a typo in your command the -source was my_drp_bufgce/I)

 

Avrum

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Adventurer
Adventurer
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Registered: ‎06-25-2015

Re: Best way to divide a clock by two

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@avrumw, Thank you. When specifying the source, why are there two [get_pins...]. Is this specifying to and from? For instance, clock path xxyyzz goes from drp_bufgce/I to drp_bufgce/O. And is this why the name does not matter as I am specifying the name of the path from the master clk to generated clk. Thank you for your time.

 

Adam

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Historian
Historian
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Registered: ‎01-23-2009

Re: Best way to divide a clock by two

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The create_generated_clock (as it's name implies) creates a generated clock.

 

A generated clock is a clock that derives most of it's attributes from a source clock. So this command says

  - Create a new generated clock (create_clock)

  - the name of the clock is xxyyzz - this is the name it will be given in the clock database in Vivado (-name xxyyzz)

  - the new clock is derived from the clock that is carried on the pin drp_bufgce/I (-source [get_pins drp_bufgce/I])

  - the new pin is attached to (i.e. created on) the pin drp_bufgce/O ([get_pins drp_bufgce/O]);

     - the attach point of the create_generated_clock command is the command line element without a -<option> before it (i.e. no -name or -source or -divide_by or -duty_cycle)

 

This is not a clock "path" - there is no such thing. This is a clock; it is defining the concept of a periodic signal with certain attributes. This clock is then used as part of static timing analysis to analyze the timing on data paths that use this clock as the clock of the startpoint and/or endpoint of the path.

 

Avrum

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Adventurer
Adventurer
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Registered: ‎06-25-2015

Re: Best way to divide a clock by two

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Thank you very much for this explanation. 

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Explorer
Explorer
1,872 Views
Registered: ‎06-09-2018

Re: Best way to divide a clock by two

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@avrumw

 

thanks for clear explanations, if i want use "edit timing constraints" option in vivado i encounter with more options (specified in below image) can you explain this options : master pin, master clk, source objects and don't override clks ... (-add) ? 

Capture.PNG
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Historian
Historian
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Registered: ‎01-23-2009

Re: Best way to divide a clock by two

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can you explain this options : master pin, master clk, source objects and don't override clks ... (-add) ? 

 

The "Master pin (source)" is the name of a pin that carries the base clock. This is the equivalent of the "-source" option in the Tcl command (create_generated_clock). This can be any pin upstream from the clock modifying block, but in general it is recommended to use the input pin of the clock modifying bock itself - so, in this case, the /I pin of the BUFGCE. The wizard appears to limit you to a pin - the create_generated_clock command can also use a net for this option (although the pin is still recommended).

 

The "Master clock" is rarely used. This is only needed in the (rare) case where the -source pin is carrying more than one clock. In this case, this option (using a get_clocks command) indicates which of the multiple clocks on the -source pin/net is the one to use. This option can never be used alone - the -source option is required.

 

And this is an important fact - pins, ports and nets in Vivado can carry more than one clock. There are multiple ways of doing this. One way is when we have a clock MUX (a BUFGMUX, or even a fabric MUX, but the latter is not recommended). If both inputs of the BUFGMUX carry a clock, then the output of the BUFGMUX (and all pins/nets downstream from it) carry both clocks. If one of these pins/nets is used as a -source for a create_generated_clock, then you need to specify which clock that it carries to use. 

 

The "Source Objects" are the ports, pins or nets to which the new clock is to be attached - this is the unnamed option of the create_generated_clock command. The new clock will be attached to this point, and will propagate to all pins/nets downstream from this point. 

 

The "Do not override clocks..." option is the -add option of the create_generated_clocks command. Normally when you attach a clock to a pin/port/net, the new clock overrides any existing clock on that port/pin/net. So, for example, before you execute a create_generated_clock, assuming a create_clock was performed on some upstream port/pin/net of the BUFGCE, then the output of the BUFGCE will carry that clock (clocks propagate through combinatorial cells and buffers). However, once you use a create_generated_clock on the output of the BUFGCE, the new clock will override the one that is already there, and only the new clock will propagate downstream.  However, if you use the -add option, the new clock will not override the old one, but both will remain and propagate downstream to all pins/ports/nets. This is the other way of getting multiple clocks on a pin/port/net; use a create_clock -add or a create_generated_clock -add on a pin/port/net that already has a clock on it.

 

Avrum

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Explorer
Explorer
1,829 Views
Registered: ‎06-09-2018

Re: Best way to divide a clock by two

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@avrumw

 

for example in your method "source object" is my_bufgce? 

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Historian
Historian
1,823 Views
Registered: ‎01-23-2009

Re: Best way to divide a clock by two

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for example in your method "source object" is my_bufgce? 

 

First, you must understand that an "object" from the Vivado point of view is a Vivado Design Database Object. The primary objects are clocks, pins, ports, nets and cells (there are also LOTS and LOTS of other kinds of objects).

 

Each command specifies which kind of objects can be used for each option.

 

For the create_generated_clock command, the source object (the option without a -<prefix>) is the clock attachment point. From the documentation for the create_generated_clock (type "help create_generated_clock" in the Tcl window in Vivado), this option can be of type pin, port or net. This is the point that the new clock (the generated clock) is attached to. This point and all points downstream (unless overridden by another create_clock or create_generated_clock without the -add option) will carry this new clock.

 

Conventionally, you attach the new clock to the output pin of the clock modifying cell. In this example, it would be the O pin of the BUFGCE.

 

Avrum

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