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smilee008
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Registered: ‎04-11-2013

Bus macros vs Partition Pins

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Hello,

 

I am learning about Partial reconfiguration and I have a few questions, for which I couldn't find an answer.

My first problem:

In the earlier versions, there were bus macros used between the static part and the reconfigurable part. In the newer versions, the partition pins were introduced. Unfortunately I couldn't find a detailed description, what is the difference and why the Partition pins are better?

 

My other problem is connected to the previous problem as well:

With the bus macros, a part of the reconfigurable area were "lost", because there can't be static, nor dinamic part.(If I am right, but correct me, if not.) I would be interested in the size of the "lost" part. Is there any doucment about it, or can this be mesaured somehow? How is this lost area is affected by the parttion pins?

 

I hope, I described my problem clearly and that someone can answer my questions. :) Tanks in advance!

 

SmiLee008

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woodsd
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

You are correct that Bus Macros are no longer needed.  Bus Macros were a hard macro that had to be included with your design.  They were also a fixed shape that spanned two slices.  These limitations were addressed with the introduction or Partition Pins (or also referred to as Proxy LUTs).  A Partition Pin is single LUT1 that is inserted by NGDBuild on the Reconfigurable Partition (RP), and is used as the connection point between Static and the RP.

 

A Partition Pin (or LUT1) will be created for every pin on your RP (except global inputs like clocks), so if you have 100 pins you can assume your design will increase by a 100 Luts.  However, this is spearate from the requirement that no Static logic an be placed within the Reconfigurable region (AREA_GROUP).  The number of resources resticted from Static is entirely dependent on the RP's AREA_GROUP RANGE constraints.  If the AREA_GROUP is only large enough to contain the largest version of the reconfiguable partition, then the amount of resources not useable by Static is minimal compared to how the design would be placed without PR.  

 

Hope this makes sense and helps you out!

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woodsd
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

You are correct that Bus Macros are no longer needed.  Bus Macros were a hard macro that had to be included with your design.  They were also a fixed shape that spanned two slices.  These limitations were addressed with the introduction or Partition Pins (or also referred to as Proxy LUTs).  A Partition Pin is single LUT1 that is inserted by NGDBuild on the Reconfigurable Partition (RP), and is used as the connection point between Static and the RP.

 

A Partition Pin (or LUT1) will be created for every pin on your RP (except global inputs like clocks), so if you have 100 pins you can assume your design will increase by a 100 Luts.  However, this is spearate from the requirement that no Static logic an be placed within the Reconfigurable region (AREA_GROUP).  The number of resources resticted from Static is entirely dependent on the RP's AREA_GROUP RANGE constraints.  If the AREA_GROUP is only large enough to contain the largest version of the reconfiguable partition, then the amount of resources not useable by Static is minimal compared to how the design would be placed without PR.  

 

Hope this makes sense and helps you out!

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smilee008
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Registered: ‎04-11-2013

Thanks a lot, it really helped!

 

So a partition Pin is a single LUT. The bus macros also could be measured by LUT spaces?

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woodsd
Xilinx Employee
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Registered: ‎04-16-2008

I believe so, but to be honest I can't recall 100%.  I believe there two luts in each macro (one LUT in Static, and one LUT in the reconfigurable partiton).  This would not only double the resources, but greatly affect timing aross this interface as well. 

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