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shany04
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Registered: ‎08-13-2013

Can I assign a new module to the partial reconfiguration region?

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Suppose that my design has a partial reconfiguration region "A" and two modules for this region, A1 and A2.

I can build the project using PlanAhead to get the full bitfile and two partial bitfile, A1.bit and A2.bit.

But this process is really time costy and make cost several hours.

 

If I have another choice, A3, for the partial reconfiguration region, can I just compile A3 to get A3.bit?

Because I have already builded the project with A1 and A2. If I build the whole project again, it will cost another several hours...

Can I just work on some process for A3 to get proper partial bitfile for A3?

 

Thanks!

 

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woodsd
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

Given you example, you should already have two configurations complete (config_A1 and config_A2).  Config_A1 would have implemented the entire design.  Config_A2 would have imported Top (Static) from config_A1. You can add in a new RM (A3) and setup config_A3 to import static from config_A1 and implement the new RM A3.

 

This will be a full design implementation to get A3 implemented, but you don't have to rerun A1 and A2 as long as you import Static from A1.  Make sure you run pr_verify on Config_A1, Config_A2, and Config_A3 when complete.

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woodsd
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

Given you example, you should already have two configurations complete (config_A1 and config_A2).  Config_A1 would have implemented the entire design.  Config_A2 would have imported Top (Static) from config_A1. You can add in a new RM (A3) and setup config_A3 to import static from config_A1 and implement the new RM A3.

 

This will be a full design implementation to get A3 implemented, but you don't have to rerun A1 and A2 as long as you import Static from A1.  Make sure you run pr_verify on Config_A1, Config_A2, and Config_A3 when complete.

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vemulad
Xilinx Employee
Xilinx Employee
11,785 Views
Registered: ‎09-20-2012

Hi Shan,

 

I hope your query is answered.

 

If yes, please mark the helpful post as solution.

 

Cheers,

Deepika.

Thanks,
Deepika.
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shany04
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Registered: ‎08-13-2013

Thanks for your reply. But I have another problem.

As you said, I have already got config_A1 and config_A2.

If someone else want to give me another RM(A3) and only want to give me the partial bitfile instead of .v file and .ngc file, how can that work?

At the same time, I donot want to give him the static logic.

Can I just give him the RM place information, such as from X3Y4 to X7Y9? and some interface information.

He can build a PR project with A3 and random static logic with the same interface as ours.

Then he can just give the A3.bitfile (partial bitfile) to me.

 

Will this work? Thanks very much.

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woodsd
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

No, this flow will not work.  You must import Static to make the configurations compatible in HW. There are two reasons you must do this.

 

1. The Proxy Logic (LUT) locations must be consistent between all configurations.  These LUTs are inferred on every port of the RM (excecpt on dedicated connections like clocks), and provide the connection between the RM and Static.  If these locations are not the same between two configurations, the routing will not connect up correctly when reconfigured.  PR_VERIFY checks that these locations are all the same.

 

2. While the RM placement and routing is contained to the AREA_GROUP, static routing can use resources in the RP region.  This is another reason why Static has to be imported from one configuration to the next. If a static routed went through a reconfigurable frame in one RM, but not another, the static would be broken during reconfiguration.  

You also need to consider routes that are not in the RM AREA_GROUP, but that use resources in the same frames as reconfigurable module.

 

We are aware of the usefullness of the the type of flow you are suggesting, and we are looking to support this Vivado sometime in the future.  This could allow for an out-of-context imlpementation of new or third party RMs, once Static has been established, by providing data from the static implementation.

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