09-08-2019 10:02 PM - edited 09-08-2019 11:36 PM
I'm not planning to use the Dynamic PR flow and no partial bit file, just use PR as a Hiearchical design to get a single bitstream.
Vivado 2019.1 Ultrascale+
I want the greybox/blackbox PR to have access physical resources (PINs, Quad GTYs) directly.
I understood the greybox feature adds LUTs and that breaks the IO wizard or GTYs IP core contained in the PR.
Is there a way to stop the inference of these LUTs and just let them disconnected to implement the static logic first?
09-08-2019 11:20 PM
Could you try to include GT and FPGA ports into Dynamic region directly?
09-09-2019 01:05 AM
Forgetting the greybox attribute, what do you mean?
I have to expose all the PR module's modports connected to a physical PIN in the static logic otherwise at synthesize, those ports aren't connected.
09-09-2019 01:33 AM
You are creating a PR design, though you don't partial bit file.
In the PR design, GT related logic should be placed in static region, and in RM NO logic conneting the GT in static?
The tools handle all the unused RM ports by inserting a LUT1 buffer within the RM, so evening you remove the LUT in grey box, it will be added automatically by tool.