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Visitor vasu123@
Visitor
430 Views
Registered: ‎10-25-2018

Can someone check my code to design a 16 bit 4*1mux using data implementation style. I have included the design source code, constraint file and the test bench file

Design source:

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4_1 is
    Port ( i0 : in STD_LOGIC_VECTOR(15 DOWNTO 0);
           i1 : in STD_LOGIC_VECTOR(15 DOWNTO 0);
           i2 : in STD_LOGIC_VECTOR(15 DOWNTO 0);
           i3 : in STD_LOGIC_VECTOR(15 DOWNTO 0);
           s0 : in STD_LOGIC;
           s1 : in STD_LOGIC;
           z : out STD_LOGIC_VECTOR(15 DOWNTO 0));
end mux4_1;

architecture dataflow of mux4_1 is

begin
z<=i0 WHEN  s0<= '0' and s1<='0';
z<=i1 WHEN  s0<= '0' and s1<='1';
z<=i2 WHEN  s0<= '1' and s1<='0';
z<=i3 WHEN  s0<= '1' and s1<='1';


end dataflow;

--------------------------------------------------------------

constraint file:

 

## Switches
set_property PACKAGE_PIN V17 [get_ports {i0}]
set_property IOSTANDARD LVCMOS33 [get_ports {i0}]
set_property PACKAGE_PIN W16 [get_ports {i1}]
set_property IOSTANDARD LVCMOS33 [get_ports {i1}]
set_property PACKAGE_PIN V15 [get_ports {i2}]
set_property IOSTANDARD LVCMOS33 [get_ports {i2}]
set_property PACKAGE_PIN W14 [get_ports {i3}]
set_property IOSTANDARD LVCMOS33 [get_ports {i3}]
set_property PACKAGE_PIN T2 [get_ports {s0}]
set_property IOSTANDARD LVCMOS33 [get_ports {s0}]
set_property PACKAGE_PIN R2 [get_ports {s1}]
set_property IOSTANDARD LVCMOS33 [get_ports {s1}]

 

## LEDs
set_property PACKAGE_PIN U16 [get_ports {z}]
set_property IOSTANDARD LVCMOS33 [get_ports {z}]

-----------------------------------------------------------

test bench code:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux4_1_tb is
--  Port ( );
end mux4_1_tb;

architecture dataflow of mux4_1_tb is
COMPONENT mux4_1 is
PORT (i0 : in STD_LOGIC_VECTOR(15 DOWNTO 0);
 i1: in STD_LOGIC_VECTOR(15 DOWNTO 0);
 i2: in STD_LOGIC_VECTOR(15 DOWNTO 0);
 i3: in STD_LOGIC_VECTOR(15 DOWNTO 0);
s0: in STD_LOGIC;
s1: in STD_LOGIC;
z : out STD_LOGIC_VECTOR(15 DOWNTO 0));
END COMPONENT;

signal i0,i1,i2,i3:    STD_LOGIC_VECTOR(15 DOWNTO 0);
signal s0,s1: STD_LOGIC;
signal z:    STD_LOGIC_VECTOR(15 DOWNTO 0);

begin

uut: mux4_1 PORT MAP (
i0,i1,i2,i3,s0,s1,z
);

i0 <= "0000000000000000";
i1 <= "1000000000000110";
i2 <= "1000000000000110";
i3 <= "1000000000000110";
s0 <= '0';
s1 <= '0';


i0 <= "1000000000000000";
i1 <= "0000000000000110";
i2 <= "0000000000000110";
i3 <= "0000000000000110";
s0 <= '0';
s1 <= '0';


i0 <= "1111111111111111";
i1 <= "0000000000000110";
i2 <= "0000000000000110";
i3 <= "0000000000000110";
s0 <= '0';
s1 <= '0';


i0 <= "1000001100000000";
i1 <= "0000000000000000";
i2 <= "1000000000000110";
i3 <= "1000000000000110";
s0 <= '0';
s1 <= '1';


i0 <= "0000000000000000";
i1 <= "1000000000000110";
i2 <= "0000000000000110";
i3 <= "0000000000000110";
s0 <= '0';
s1 <= '1';


i0 <= "0111111111100000";
i1 <= "1111111111111111";
i2 <= "0000000000000110";
i3 <= "0000000000000110";
s0 <= '0';
s1 <= '1';

i0 <= "1000000000000000";
i1 <= "1000000000000110";
i2 <= "0000000000000000";
i3 <= "1000000000000110";
s0 <= '1';
s1 <= '0';


i0 <= "0000000000000000";
i1 <= "0100000000000110";
i2 <= "1110000000000110";
i3 <= "0000000000000110";
s0 <= '1';
s1 <= '0';


i0 <= "0011100000001111";
i1 <= "0000000000000110";
i2 <= "1111111111111111";
i3 <= "0000000000000110";
s0 <= '1';
s1 <= '0';

i0 <= "1000000000000000";
i1 <= "1000000000000110";
i2 <= "1000000000000110";
i3 <= "0000000000000110";
s0 <= '1';
s1 <= '1';


i0 <= "1000000000000000";
i1 <= "0000000000000110";
i2 <= "0000000000000110";
i3 <= "1111000000000110";
s0 <= '1';
s1 <= '1';


i0 <= "0000001111111111";
i1 <= "0000000000000110";
i2 <= "0000000000000110";
i3 <= "1111111111111111";
s0 <= '1';
s1 <= '1';


end dataflow;

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1 Reply
399 Views
Registered: ‎06-21-2017

Re: Can someone check my code to design a 16 bit 4*1mux using data implementation style. I have included the design source code, constraint file and the test bench file

What errors do you get?  Can you simulate?  Can you synthesize?  If you simulate, does this do what you expect? 

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