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Observer jamesba-bbc
Observer
12,341 Views
Registered: ‎07-27-2011

Cannot place differential clock input pin on VC707

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I'm trying to synthesise a design for the VC707 evaluation board. The design makes use of the AXI to PCIe Bridge IP Core, which requires a REFCLK input which carries the PCIe reference clock recovered from the connector. On the VC707 this clock appears to come in on a differential pair on pins AB8 and AB7.

 

In my design I have a top-level with an IBUFGDS generating my REFCLOCK signal from my sys_clk_p and sys_clk_n top level ports.

 

REFCLK_ibufds : IBUFGDS
port map (
O => REFCLK,
I => sys_clk_p,
IB => sys_clk_n
);

 

In my XDC I try to use the following line to assign this clock input to a pin:

 

set_property PACKAGE_PIN AB8 [get_ports sys_clk_p]

 

Vivado refuses to allow this pin assigning, claiming that it cannot legally place REFCLK_ibufds at the location IPAD_X2Y70 because this would result in an illegal location for the other half of the differential pair, sys_clk_n.

 

Nonetheless, AB8 is the pin that the VC707 schematic says is an MGTREFCLK1P, and its pair should be AB7 which is MGTREFCLK1N, so I can't see what the problem is.

 

Can anyone help me with this?

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Observer jamesba-bbc
Observer
18,009 Views
Registered: ‎07-27-2011

Re: Cannot place differential clock input pin on VC707

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I have now solved this problem.

 

I needed to instantiate an IBUFDS_GTE2 instead of an IBUFDS.

7 Replies
Scholar austin
Scholar
12,340 Views
Registered: ‎02-27-2008

Re: Cannot place differential clock input pin on VC707

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j,

 

You are confusing the dedicated clock pins for the MGT with the programmable fabric clock pins.


The MGT pins are dedicated, and you do not need to  conctrain them (or even note them in the verilog/vhdl) as they are deidcated, and go directly into the MGT.

 

That reference is then use to train the PLL's (get them close) to the right frequency.  An output clock fromt he MGT (the receive data clock IS what you then need to use in your RTL code, as that clock is the actual received clock which matches the received data.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Instructor
Instructor
12,337 Views
Registered: ‎08-14-2007

Re: Cannot place differential clock input pin on VC707

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I seem to remember that (at least for Virtex 5) you could instantiate an IBUFDS (but not IBUFGDS) for

the reference clock pair.  There are of course restrictions on how you connect the output of that

differential receiver.

-- Gabor
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Observer jamesba-bbc
Observer
12,314 Views
Registered: ‎07-27-2011

Re: Cannot place differential clock input pin on VC707

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Ok, thanks.

 

What does that mean I should be doing here? The AXI PCIe Bridge has a REFCLOCK input port, which is supposed to be the reference clock from the PCIe connector. Presumably I need to feed some sort of apropriate clock signal into that one? Do you know which pins I should be sourcing that clock from?

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Observer jamesba-bbc
Observer
12,312 Views
Registered: ‎07-27-2011

Re: Cannot place differential clock input pin on VC707

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Ok, further issue. 

 

As far as I can tell according to the VC707 USerguide the PCIe connections from the connector are routed to the GTXE2_CHANNEL_X0Y12-19. As far as I can tell from looking at the device layout in Vivado (is there a better way of checking this?) these should connect to PCIE_X0Y1, but the only PCIe embedded blocks which the IP generator will allow me to generate the AXI PCIe bridge for are PCIE_X1Y0 and PCIE_X1Y1. I wonder if this is related?

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Observer jamesba-bbc
Observer
12,305 Views
Registered: ‎07-27-2011

Re: Cannot place differential clock input pin on VC707

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Ignore that, it seems to be a misprint in the User Guide. 

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Observer jamesba-bbc
Observer
18,010 Views
Registered: ‎07-27-2011

Re: Cannot place differential clock input pin on VC707

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I have now solved this problem.

 

I needed to instantiate an IBUFDS_GTE2 instead of an IBUFDS.

Scholar austin
Scholar
12,296 Views
Registered: ‎02-27-2008

Re: Cannot place differential clock input pin on VC707

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j,

 

Thank you for posting the solution.

 

I was trying to tell you that the MGT's have their own special clocking resources.  I apologize if I wasn't very helpful going about it.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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