07-30-2020 01:47 PM - edited 07-30-2020 01:48 PM
Hi everyone, I have a design implementation by partial reconfiguration using a virtex-7 board. My doubt is: Is possible run the reconfigurable logic in the FPGA and the static logic in a ASIC chip? Something similiar to a hybrid ASIC and FPGA architecture.
07-31-2020 03:18 PM
Since a few things like global clocking resources (MMCMs, BUFGs...) and all IOs are required to be in the static for 7-Series designs, this would not be possible.
08-03-2020 04:22 PM
I think that I formulated the question in the wrong way. My aim is to do something similar to partial reconfiguration. I would like to construct a system with a few parts running in a FPGA and others running in an ASIC and connect the netlist of both them. Is this possible?
08-07-2020 03:43 PM
Using FPGAs within a system with other chips such as ASICs is common, but the Dynamic Function eXchange feature (formerly Partial Reconfiguration) is applied to a single specific supported part. It generates bitfiles and partial bitfiles for an individual part.