07-05-2019 08:04 AM
I will be feeding my Artix-7 chip with a single 20Mhz clock source. From this I need to derive four clocks at 320Mhz, 160MHz, 80Mhz and 1Mhz.
The 1Mhz is causing me grief, as this is below the minimum (~5Mhz) output limit of the Artix-7 MMcM block.
Can anyone advise the most effective method of generating that last frequency. Clearly a simple counter off one of the other clocks could be used, but perhaps there is a more elegant solution, and one that will lend itself to accurate timing analysis later in the design.
07-05-2019 10:13 AM - edited 07-05-2019 10:14 AM
Take a look at this post (and the referenced posts within it) for using the BUFGCE to generate a "decimated" clock. You can generate your 1MHz clock from the 80MHz clock with a count down counter (from 79 to 0) and enabling the BUFGCE on the clock where it is 0 (or the clock after if you want to put an extra FF on that path).
The only caveat is that the duty cycle of this clock will be very uneven (high for 1/2 of an 80MHz clock period every 1MHz - so 1/160). This is not a problem unless you are planning to use the falling edge of this clock for something (either internally or using an ODDR/IDDR or OSERDES/ISERDES in DDR mode). If the clock is merely used as a rising edge clock, then it is fine.
The post referenced at the end of that post will show you how to place a create_generated_clock constraint on the output of the BUFGCE.
07-05-2019 10:54 AM
Often, when someone says they want a slow clock, what they really want is a toggle.
A toggle is a signal that looks like a clock but is not a clock because it is not routed in the FPGA clock tree. Using a toggle instead of a slow clock will often simplify coding and save the precious clocking resources of the FPGA.
In the following thread, I give more description and usage of the toggle.