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Registered: ‎01-05-2017

DFX Tutorials for Versal

Xilinx has released 8 Vivado Versal DFX tutorials in github. They are available in public Xilinx Git now.

If you have any feedback on these tutorials please open a new thread and we will look into it.

Covered topics:

Single Reconfigurable Partition Design using Block Design Container 
This tutorial introduces the Block Design Container (BDC) feature in Vivado and how it can be leveraged to create DFX designs in Versal.

Multiple Reconfigurable Partitions Design using Block Design Container 
This tutorial demonstrates how to create a design with multiple reconfigurable partitions using BDC.

Clock Region Shared by two Reconfigurable Partitions 
This tutorial demonstrates a floorplan in Versal that allows for the sharing of a clock region b/w two reconfigurable partitions.

JTAG and HSDP based debugging for Versal DFX Designs 
This tutorial demonstrates a debug methodology for DFX designs in Versal using JTAG and HSDP.

Embedded IOBs inside the Reconfigurable Partition 
This tutorial demonstrates a methodology to insert embedded IOBs inside reconfigurable partition using utility buffer IP in Vivado.

NoC connections in DFX designs 
This tutorial introduces multiple NoC connectivity options for DFX designs to transfer data b/w static and reconfigurable partition.

Update BD Boundary for DFX Designs 
If one of the reconfigurable module is modified to add or remove ports, all the remaining reconfigurable modules associated with that partition can also be updated to match with exact same ports using the command called "update_bd_boundaries".

VNOC column sharing b/w multiple RPs 
This design demonstrates that VNOC clock tiles can be shared between two reconfigurable partitions. VNOC clock tiles are automatically included in the clock routing footprint of the reconfigurable partition by the tool. 


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