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6,932 Views
Registered: ‎01-13-2018

Default values of input and output in VHDL - 2008

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Is it possible to define the default values of input and outputs where we define the I/O ports of the entity ? instead of defining them by initializing signals with default value and then assign to the outputs in architecture ? 

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7,336 Views
Registered: ‎01-08-2012

Re: Default values of input and output in VHDL - 2008

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Yes, this is possible for both Inputs and Outputs in the current version of VHDL as well as older VHDL versions going back to 1993.  (Possibly 1987 as well, but I don't have a copy of that standard.)

 

See section 6.5 of the VHDL LRM, particularly 6.5.6.3 (Port clauses).

 

The syntax looks like this:

entity foo is
    port (
        bar1    : in  std_logic := '0';
        bar2    : out std_logic := '0'
    );
end entity foo;
entity foo2 is
generic (
g_init_val : std_logic := '1'
); port ( bar1 : in std_logic := g_init_val; bar2 : out std_logic := g_init_val;
bar3 : out std_logic_vector(3 downto 0) := (others => g_init_val) ); end entity foo2;

 

Input ports without a default value must be mapped to something (not "open") in a port map in the instantiation.

 

Input ports with an default value may be unmapped (or mapped to open) in a port map.  In this case (and this case only), they keep the default value specified.  In all other cases the default value is ignored.

 

Output ports may have an initial value specified.  This should have roughly the same effect as a signal initialisation inside the architecture.

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1 Reply
7,337 Views
Registered: ‎01-08-2012

Re: Default values of input and output in VHDL - 2008

Jump to solution

Yes, this is possible for both Inputs and Outputs in the current version of VHDL as well as older VHDL versions going back to 1993.  (Possibly 1987 as well, but I don't have a copy of that standard.)

 

See section 6.5 of the VHDL LRM, particularly 6.5.6.3 (Port clauses).

 

The syntax looks like this:

entity foo is
    port (
        bar1    : in  std_logic := '0';
        bar2    : out std_logic := '0'
    );
end entity foo;
entity foo2 is
generic (
g_init_val : std_logic := '1'
); port ( bar1 : in std_logic := g_init_val; bar2 : out std_logic := g_init_val;
bar3 : out std_logic_vector(3 downto 0) := (others => g_init_val) ); end entity foo2;

 

Input ports without a default value must be mapped to something (not "open") in a port map in the instantiation.

 

Input ports with an default value may be unmapped (or mapped to open) in a port map.  In this case (and this case only), they keep the default value specified.  In all other cases the default value is ignored.

 

Output ports may have an initial value specified.  This should have roughly the same effect as a signal initialisation inside the architecture.

View solution in original post