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Design Custom Iterconnect IP

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Observer
Posts: 13
Registered: ‎07-25-2016

Design Custom Iterconnect IP

Hi everyone,

 

I'm trying to design a component to "emulate" the functionality of the AXI interconnect module, but with some added features I need. I'm working in Vivado 2017.2.

 

Without going into the details, I've created a custom IP (design_1_v1_0) with the required slave and master AXI interfaces. Now I'm trying to simulate the design using VIP modules, as in figure:

 

block_design.jpg

As you can see, there's an error showing up in the message window:

[BD 41-703] Peripheral </axi_vip_mem/S_AXI/Reg> is mapped into master segment </axi_vip_kernel/Master_AXI/SEG_axi_vip_mem_Reg>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.

The address editor looks something like this instead:

block_design_addr_editor.jpg

 

I believe my IP is correct, but how do I fix/avoid that error? How is the tool able to detect that error?

 

Thank you in advance for any suggestion,

Best,

 

Stefano

 

Xilinx Employee
Posts: 2,061
Registered: ‎11-09-2015

Re: Design Custom Iterconnect IP

Hi @stefanoribes,

 

My guess is that there is some parameters that are propagated through the AXI interconnect and this is not done in you case.

 

You should start by re-creating the AXI interconnect with the IPs under the hook (axi cross bar, AXI Data Width Converter).

Use an AXI interconnect and then look what is inside. Then replace the Interconnect with the IPs you see inside. Then, if it is working, replace each small ips one by one.

 

Regards,

 

Florent

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Observer
Posts: 13
Registered: ‎07-25-2016

Re: Design Custom Iterconnect IP

Hi @florentw,

 

Thank you for the fast reply. I'll try to include the Data Width Convert IP in my design first and see what happens.

 

The problem I see in this approach is that I cannot really look at the sub-IPs' code (obviously). May I ask what kind of parameters do you mean? Are the ones configurable through the GUI? If so, shall my verilog code (and later my packaged IP) include them as well?

 

My first idea was actually to use one or several IPs from HLS, so no (or as less as possible) generic parameters involved. In this way I would just use bare AXI connections.

 

Thanks, Best,

 

Stefano

Xilinx Employee
Posts: 2,061
Registered: ‎11-09-2015

Re: Design Custom Iterconnect IP

Hi @stefanoribes,

 

May I ask what kind of parameters do you mean? Are the ones configurable through the GUI? If so, shall my verilog code (and later my packaged IP) include them as well?

-> Not I am not talking about these parameters... or not really because some time they are configured through the gui. I am talking about the parameters associated with an interface. For example if you click in an interface on your bd, in the left you should have a properties window. This parameters are usually propagated using hidden commands (which start with ipx::).

However it is just a guess that this is your issue. I could also be a totally different reason

 

Regards,

 

Florent

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