EMIO Routing of GPIO to External Ports for both Input and Output
I am having difficulty understanding how to break out GPIO using EMIO through the PL to external ports. In the attached block diagram, you can see the original design utilizes all of the EMIO GPIO as outputs (originally 30 EMIO GPIO are utilized, I expanded this to 31 EMIO to make room for an extra input. All of the original outputs are connected to emio_gpio_o[30:0]. This bus (highlighted) is then sliced so that multiple busses can be formed that map to pins on the low speed expansion header. I want to use the EMIO GPIO to add a single input port through one of the free pins in the same low speed expansion header. I do not know how to wire an input port which connects to the original 31 bit wide bus. When I try to connect a wire in the block diagram to the emio_gpio_i[30:0] I am not sure how to direct my input port to a single bit (specifically EMIO 31).
Fundamentally, I am misunderstanding something, because I don't understand why the EMIO get broken down into 3 busses, (input, output, and tri). I would like to know how to dedicate some of the total number of EMIO gpio to inputs, some to outputs, and some as tri. I would think a single bus would exist coming from the PS which can then be sliced and assigned to different ports, may they be inputs, outputs or tri. If someone can help clarify this concept it would be greatly appreciated!