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laksh0070
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3,662 Views
Registered: ‎08-02-2018

ERROR: indexed name is not a std_logic_vector

I was recently trying to make a 4x1 mux using a 2x1 mux and i encountered an error while simulating the test bench.

Here's the code for it and a pic for reference of the error i am facing.

 

2x1 mux code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUX2_1 is
    Port ( I0 : in STD_LOGIC;
           I1 : in STD_LOGIC;
           S : in STD_LOGIC;
           Y : out STD_LOGIC);
end MUX2_1;

architecture Behavioral of MUX2_1 is
SIGNAL SBAR:STD_LOGIC;

begin
SBAR<=not S;

Y<=(S AND I1) OR (SBAR AND I0);

end Behavioral;

4x1 code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX4_1 is
    Port ( I : in STD_LOGIC_VECTOR (0 to 3);
           S : in STD_LOGIC_VECTOR (0 to 1);
           Y : out STD_LOGIC);
end MUX4_1;


architecture Behavioral of MUX4_1 is
COMPONENT MUX2_1 is


    Port ( I0 : in STD_LOGIC;
           I1 : in STD_LOGIC;
           S : in STD_LOGIC;
           Y : out STD_LOGIC);
END COMPONENT;

SIGNAL A,B:STD_LOGIC;

begin
M1: MUX2_1 PORT MAP(I0=>I(0),I1=>I(1),S=>S(0),Y=>A);
M2: MUX2_1 PORT MAP(I0=>I(2),I1=>I(3),S=>S(0),Y=>B);
M3: MUX2_1 PORT MAP(I0=>A,I1=>B,S=>S(1),Y=>Y);

end Behavioral;

4x1 test bench

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX4_1_TB is
--  Port ( );
end MUX4_1_TB;

architecture Behavioral of MUX4_1_TB is
COMPONENT MUX4_1 is
    Port ( I : in STD_LOGIC_VECTOR (0 to 3);
       S : in STD_LOGIC_VECTOR (0 to 1);
       Y : out STD_LOGIC);
END COMPONENT;

SIGNAL I_TB :STD_LOGIC_VECTOR (0 to 3);
SIGNAL S_TB :STD_LOGIC_VECTOR (0 to 1);
SIGNAL Y_TB : STD_LOGIC;

begin

M1:MUX4_1 PORT MAP(I_TB(0),I_TB(1),I_TB(2),I_TB(3),S_TB(0),S_TB(1),Y_TB);

PROCESS

BEGIN

I_TB<="0000";
S_TB<="00";
WAIT FOR 5 NS;

I_TB<="0001";
S_TB<="01";
WAIT FOR 5 NS;

I_TB<="0011";
S_TB<="10";
WAIT FOR 5 NS;

I_TB<="1000";
S_TB<="00";
WAIT FOR 5 NS;

I_TB<="0100";
S_TB<="01";
WAIT FOR 5 NS;

I_TB<="0010";
S_TB<="10";
WAIT FOR 5 NS;

END PROCESS;
end Behavioral;

 

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1 Reply
kenkovaa
Contributor
Contributor
3,629 Views
Registered: ‎09-14-2017

Hi,

 

The instantation of the mux is incorrect in the testbench, you could figure that out from the indicated logfile:

ERROR: [VRFC 10-37] mux4_1 has only 3 ports [xxxx/project_4/project_4.srcs/sources_1/new/muxtb.vhd:21]

 

The correct way would be:

--M1:MUX4_1 PORT MAP(I_TB(0),I_TB(1),I_TB(2),I_TB(3),S_TB(0),S_TB(1),Y_TB);
M1:MUX4_1 PORT MAP(I_TB,S_TB,Y_TB);

 

Also there are much nicer ways of writing multiplexers, one way would be (and there are many shorter ways to write this, for example using when, for loops etc.). I did not simulate this but looks correct ;)

 

architecture arch of MUX4_1 is
begin
   process (I, S)
   begin
      case S is
         when "00" => Y <= I(0);
         when "01" => Y <= I(1);
         when "10" => Y <= I(2);
         when "11" => Y <= I(3);
         when others => Y <= I(0);
      end case;
end process;
end arch;

 

--Kim