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Registered: ‎07-12-2019

Example Design in UG905: Hierarchical Design

Hi everyone,


I saw that there is an example design to "UG905: Hierarchical Design" (link), page 9, which is mentioned as "available on request".

Can anyone tell me how can I obtain the example design?



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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2019

Hi @lichengguo777,

What device family are you using?

For UltraScale/UltraScale+, we recommend using UG909 and UG947 (Vivado Design Suite User Guide: Partial Reconfiguration) since the UG905 applies to the 7 series devices.

There's a note on page 5 of UG905 in case you wanted to see it there.

We strongly recommend Top-Down flow mentioned in UG909 and UG947 for HD. This flow allows you out-of-context synthesis of individual modules, but in-context implementation with top design. This is to leverage other features like Expanded Routing, proper PPLOCs placement in context of the whole design and so on. 

If you are using the 7-series, let us know and we can go from there! If you are using the US/US+, try out those User Guides and let us know if you run into any issues!



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