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joures
Visitor
Visitor
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Registered: ‎05-06-2017

FPGA Manager Partial Reconfiguration questions

I am interested in implementing Partial Reconfiguration enabled designs on a variety of platforms for a project and i have a few questions.

It is my understanding that xdevcfg.c driver for reconfiguring (partially or completely) the PL has been deprecated in Vivado/SDx tools 2018.1 and later and that the FPGA Manager Linux Framework was adopted.

Reading up on the https://xilinx-wiki.atlassian.net wiki (specifically here and here) i have come across guides to reconfiguring the PL on a Linux-based platform but all solutions use the sysfs and CLI commands to carry out the reprogramming. I am interested in developing an application on SDSoC or Vivado SDK running in Linux that enables condition-based partial bitstream reprogramming of the PL.

  1. Is there support for partial/full bitstream reprogramming using Linux FPGA Manager API for Zynq7000 devices? If not i would like to know if and when Xilinx plans to release support for this workflow on the Zynq7000 family of devices. (I am aware of Note 2 disclaimer )
  2. Is there support for partial/full bitstream reprogramming using Linux FPGA Manager API for ZynqMP devices? If there is, where can i find a list of supported devices?
  3. Is Vivado/SDx ver. 2019.2 going to include implemented Linux FPGA Manager driver API for reprogramming the PL?
  4. How do compressed/authenticated/encrypted bitstreams tie in with the FPGA Manager framework?
  5. Lastly, does Xilinx have plans for integrating Partial Reconfiguration workflows on SDx-based projects? I noticed that in versions 2018.1 and earlier of SDx we could define a partition on which to program a specific HW coprocessor custom IP at runtime by using sds pragma partition but it was removed in later versions. Did it work by partially reconfiguring the called HW coprocessor and then programming its RP with a blank bitstream? Why was it removed?
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joaragj
Observer
Observer
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Registered: ‎09-10-2018

Bumping this question up. Can we get an answer to this? Why is there no partial reconfiguration support in Petalinux anymore? (referering to XAPP1231 which used the now depreciated devcfg interface for partial reconfiguration of the fpga in Linux).

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lowearthorbit
Scholar
Scholar
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Registered: ‎09-17-2018

FWIW...

Partial configuration has been a solution in search of a problem since the first Xilinx device in 1984.  That said, there have been some notable successes:  SEU scrubbing, PCIe tandem bitstreams, many university student masters and PhD degrees, many ACM and IEEE papers, waveform loading for SDR (and more that are trade secrets).

At no point has Xilinx gone to any great effort, as there is just no reward (no money) to make it easier, or smoother.  It remains to be used by those who are willing to spend the time and effort to get it to work.  Depending on how many devices you promise to buy, Xilinx will help you get over any problems you are having.

lowearthorbit

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