Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎07-01-2009

Fault tolerance in FPGA’s via partial reconfiguration

Hi All,


I am facing some problems relating to this topic. 

My problems are:

1)      Suppose there is an adder, and it generates a bitstream everytime it is downloaded on FPGA or when FPGA is powered on. I want to read that bitstream but I don't know how to do it.

2)      Also i heard about a command ‘bitgen’ to generate bitstream, but i don’t know how to use it.

3)      There are two tools which are used for partial reconfiguration. One is ‘ISE’ and the second is ‘Plan ahead’. But I don’t the exact steps or design flow to use it.


I would be very thankfull if anyone can provide me answers to the above questions or provide me some info.


Thanks in advance.

0 Kudos
1 Reply
Registered: ‎10-29-2007

I don't see clearly the relation of fault-tolerance and your problems.

I don't know if you understand the principle of partial reconfiguration, at power-on, the full bitstream need to be downloaded, and after that you download the correct partial bitstream to partially modify one zone in the FPGA without disturbing the rest.


To reply to 1st question: You want to read the bitstream, you want to read the bitstream once the FPGA is reconfigured or the .bit bitstream?

2st question: to use bitgen you need to have netlist files like .ncd, ...

3st question: the needed tools depend on what you want to do. I always build autonomous system in which there is a MicroBlaze who controls the partial reconfiguration process. The MicroBlaze's program automatically looks for the bitstream and reconfigure the appropriate FPGA region. So I need EDK for building MicroBlaze system.

You also need to install a special service pack called PartialFlow_xxx.

The attached files explains how to build a PR System.

0 Kudos