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Observer particle
Observer
11,588 Views
Registered: ‎01-03-2010

Frequent UCF corruption when using PlanAhead

I'm curious as to what I'm doing that PlanAhead doesn't appear to be able to handle.  Please note that the following describes usage where only PlanAhead is used to edit the constraints file--no external editors are used so as to prevent interference.  I use PlanAhead for pairing I/O ports with actual I/O sites on an FPGA package.  When I add a new port in my top level module in ISE Project Navigator and save the file, PlanAhead properly detects the change and adds that port after asking me if I want to reload the file.

 

However, when I make any change that removes assigned pins such as reducing the width of a bus or removing a pin/bus entirely, PlanAhead flips entirely.  From that point on, it will randomly forget pins or entire busses' assignments.  It will ignore newly mapped pins.  If you look at the UCF it generates with notepad, you'll find that old pins that don't even exist anymore (the ones removed) are still in the UCF file.  Others are defined multiple times.  Some are missing entirely.

 

I'm shocked that an industrial design tool seems to have trouble doing such a basic task with any degree of reliability.  Perhaps I'm using it in a way that it wasn't intended.  If so, please help me out.  If not, what gives?

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5 Replies
Observer particle
Observer
11,548 Views
Registered: ‎01-03-2010

Re: Frequent UCF corruption when using PlanAhead

Nevermind I guess.  I decided to make my own GUI-based user constraints editor.  It works fine, runs faster, is extensible, and doesn't randomly mess up UCF files so I'll just use that.

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Visitor tom.binko
Visitor
11,465 Views
Registered: ‎03-23-2011

Re: Frequent UCF corruption when using PlanAhead

I've had the very same issue yesterday.  PlanAhead 12.4 litterally garbled up my UCF file that I tried to import.  It changed names of some nets to instances deeper than in the top level, it changed pin locations or omitted them.  Whatever reason it did it, it wouldn't implement afterwards.  This was a known good design with a good UCF that was implemented previously.  I spent an hour fixing the UCF in the text-based editor, tried to implement it, and it still gave me problems.  I haven't tried using the GUI-based constraints editor yet, I'll try that next and re-post a message if I got successful.

 

Tom

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Observer ltovey
Observer
11,324 Views
Registered: ‎03-01-2010

Re: Frequent UCF corruption when using PlanAhead

Particle,

 

Are you willing to share that editor that you made?

 

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Xilinx Employee
Xilinx Employee
11,320 Views
Registered: ‎06-16-2008

Re: Frequent UCF corruption when using PlanAhead

Hello,

 

I'm trying to decipher the issues you are having. It sounds like you are launching PlanAhead from Project Naviagtor for I/O pin placement. When doing so, a snapshot of your I/O ports and UCF constraints are passed to PlanAhead for placement. The two tools do not have any autoupdate mechanism, so when IO ports of UCF changes are made in one environment, they are not automatically passed to the other. This is pretty well documented.

 

If you are adding I/O ports in your Prject NAvigator sources, close PlanAhead and re-invoke it after your ports list has changed. After you make edits in PlanAhead close and save to update the Project Navigator UCF.

 

As far as UCF corruption, PlanAhead does try "very hard" to maintain the original format netlist, including comments. Sometimes when I/Os are removed and replaced, the tool has no idea where to write those constarints back, so it appends them at the end of the file.

 

The problems you describe do not exist when PlanAhead is used as the standalone flow management tool in place of Project Navigator. This will be the tool flow we will be promoting and developing moving forward.

 

Regards,

Brian Jackson

Software Applications

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Visitor tbinko
Visitor
11,312 Views
Registered: ‎10-02-2007

Re: Frequent UCF corruption when using PlanAhead

In order to reply to your email, I decided to try it again and re-run it under a new project.  So, I started a new project (as I did the very first time) in PlanAhead 12.4 and checked Specify  RTL Sources (unchecked Import Settings From XST), and selected my vhdl (checked Copy Sources Into Project), and selected my ucf file (checked Copy Sources Into Project).  Then I selected my part (XC3S400PQ208-5C).  The files all import correctly, and I've looked at the ucf at this point and it is the same file (no alterations). Under Synthesis, I type in the name of the top level module and leave all the other settings as they are.  The synthesis goes OK and I re-look at the ucf file and it doesn't look altered.  Then I run the implementation, and this time it completes with no errors.  I re-look at the ucf, and it doesn't look altered.  So... I can't reproduce the initial problem I got with an altered ucf file.  I guess I'm OK right now.  I'll keep my eye on it.

 

Tom

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