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296 Views
Registered: ‎04-16-2017

GT IOs in RM

Hi, 
I'm working with Partial Reconfiguration and have some issues if anyone can help with.
Target Device: Vertix UltraScale+
Vivado: 2017.3
My RM is actually bigger than my static top. My RM contains multiple SLRs and it does have a GT core (Serial Transceivers). 
PR.jpg
My RM does have SERDES I/O and Reference Clocks which I didn't expose to the Static Top but, I want to have them as IO ports so that I can set their PACKAGE_PIN property to connect them directly to the GTs. If I expose them to the Static Top then Vivado will place LUT1 over the boundaries which I don't want.

Please see the example code of my case;

module Static_Top
(
input Clk,
input Reset,
input Ena,
input [7:0] Data_in_Static,
input [7:0] Data_in_RM,
output reg [7:0] Data_out_Static,
output [7:0] Data_out_RM
);

//Static Logic
always @(posedge Clk) begin
if (Reset) begin
Data_out_Static <= 8'd0;
end
else if (Ena) begin
Data_out_Static <= Data_in_Static;
end
end


//Reconfigurable Logic
RM i_RM
(
.Clk (Clk),
.Reset (Reset),
.Ena (Ena),
.Data_in (Data_in_RM),
.Data_out (Data_out_RM)    // Rest of the IOs are not exposed here
);

endmodule

 

where RM module looks like,

module RM
(
input Clk,
input Reset,
input Ena,
input [7:0] Data_in,
output [7:0] Data_out

//Not Exposed IOs
input RefClk_p,
input RefClk_n,
input [11:0] RxSerdes_p,
input [11:0] RxSerdes_n,
output [11:0] TxSerdes_p,
output [11:0] TxSerdes_n
);

// IP instantiations and other logic is here

endmodule

 

I'm using PR Project flow, so I created the Partition Definition on the RM which made RM OOC synth run. I do have two .xdc files one for Static_Top and one for RM. In Static_Top.xdc I have defined all IO standards and package pins for Clk, Reset, Ena, Data_in_Static, Data_out_Static, Data_in_RM, and Data_out_RM. While in RM.xdc I have defined IO standards and package pins for RefClk_p, RefClk_n, RxSerdes_p, RxSerdes_n, TxSerdes_p, and TxSerdes_n. 
I have created a parent run as a GreyBox then child run for RM so it looks like this
PR1.png
I have inserted the RM.xdc using OPT_DESIGN.PRE in impl_RM run to apply LOC constraints to the RM IOs but I couldn't apply them because these IOs (RefClk_p, RefClk_n, RxSerdes_p, RxSerdes_n, TxSerdes_p, and TxSerdes_n) are actually cell pins instead of actual IOs so they don't have PACKAGE_PIN property.

According to UG947 (Page#13), we can have ISERDES, OSERDES, MGTs in the RM. 
Could anyone please explain is it a possible way to have IOs in RM without exposing them to the Top? Any suggestions or ideas?
Thanks!

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2 Replies
Moderator
Moderator
263 Views
Registered: ‎11-04-2010

Re: GT IOs in RM

Hi, uzaifsharif@yahoo.com ,

If RM contains IO ports, these RM ports should still be exposed to the top level. 

In the top level, these ports for RM should be set with io_buffer_type none.

Ex:(* io_buffer_type = “none” *) input in1;

In the RM design, all the needed Ibuf/obuf should be instantiated manually.

 

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Observer
Observer
223 Views
Registered: ‎08-15-2014

Re: GT IOs in RM

Hongh, if the top level rtl needs to have these ports defined, then for each RM that's used the top rtl would have to be modified and get recompiled. Doesn't that defeat the purpose of having the RM independent of the static top?

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