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1,379 Views
Registered: ‎06-08-2018

Generating different clock frequency for partial reconfiguration flow

Dear all 

I have a design comprised of the static part and 3 partial reconfigurable partitions.

Due to this fact that, at any given point of time, each dynamic partition of the FPGA consists of a number of modules that are plugged in and reconfigured on the fly. These modules may have varying requirements of clock frequency, which are usually not known a priori.

Also according to the Xilinx tutorial, those architectural features that are used to modify clock signals cannot be included in a partial reconfiguration partition. These include BUFG, MMCM, PLL, and DCMs.

But I think we must reprogram D and M of the DCM with partial bits, to produce different clock frequency, so we must put DCM controller in every partial reconfigurable partition, am I right?

In the other hand, we connect the output of DCM to other parts like static part or another PRs.how can I prevent changing the clock of other parts when I want to program DCM ?

Best Regards

 

 

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7 Replies
Moderator
Moderator
1,358 Views
Registered: ‎11-04-2010

Re: Generating different clock frequency for partial reconfiguration flow

What's your target device?
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1,350 Views
Registered: ‎06-08-2018

Re: Generating different clock frequency for partial reconfiguration flow

Virtex 5 XC5VLX20T-1FF323

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Scholar drjohnsmith
Scholar
1,323 Views
Registered: ‎07-09-2009

Re: Generating different clock frequency for partial reconfiguration flow

An interesting idea.

 

If you have say three none static parts in the fpga, could you allocate a different DCM output to each part ?

    then depending upon what unit you plug into the variable part, you can program its clock.

 

You then need some unit in the static part , to take in information from each none static parts, to program the dcm in the static part. 

    some sort of std_logic_vector would do nicely.  You just need to define what numbers you want to use,

 

How are you passing other information between the units, you could do with some fixed clock common to all units, and do the clock crossing in each unit,

 

Your also going to have to worry about clocking routing resources, 

       this is going to need some careful clock planning

 

as I say, an interesting problem..

  

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
1,311 Views
Registered: ‎06-08-2018

Re: Generating different clock frequency for partial reconfiguration flow

thanks for your reply but I think still there is a problem 

the DCM is in static part, so I cannot reprogram it again due to this fact that the static part must be programmed just in time in the beginning, so I don't know how can I modify clock without regenerating the bitstream of the static part 

 

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Moderator
Moderator
1,290 Views
Registered: ‎11-04-2010

Re: Generating different clock frequency for partial reconfiguration flow

Hi, @hanieh_jafarzadeh ,

Yes, in old device such as V5, DCM cannot be placed in the dynamic region. 

Maybe you can consider DCM DRP to modify the output of DCM:

https://www.xilinx.com/support/answers/39684.html

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Scholar drjohnsmith
Scholar
1,272 Views
Registered: ‎07-09-2009

Re: Generating different clock frequency for partial reconfiguration flow

was assuming using the drp of the dcm in the static region.

 

Assuming that dcm  does have the dynamic reconfiguration port

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Moderator
Moderator
1,264 Views
Registered: ‎11-04-2010

Re: Generating different clock frequency for partial reconfiguration flow

Hi, @drjohnsmith ,
I neglect it and you'are correct.
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