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Registered: ‎10-08-2012

Help in synthesis of Top level module in PR



I have been working on setting up a partial reconfiguration and have implemented the reference designs. As the reference designs came directly with netlists , I was not able to figure out how the synthesis of the top level module is done. For my project I will need a static module and a couple of reconfigurable partitions. I am having troubles with declaring the reconfigurable partions as block boxes in the top level static module and synthesisng it using ISE.  Is ISE the only way to synthesize the top level module (static logic) or kindly explain the command line method for synthesising the top level module with the blackboxes. Kindly, help me out with this.


I have attached the code ( static module being the fft4_mux and fft4_1 & fft4_2 for PR).

Kindly, help me synthesise this module


Thanking you 




David Dhas

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Xilinx Employee
Xilinx Employee
Registered: ‎04-16-2008

Although the tutorial does come with synthesized results, everything to rerun synthesis is also provided... just look in the "./Synth" directory to see the .xst project file that gets called. 


The synthesis that get run is bottom-up synthesis. As you eluded to, this means you need to have the RPs as blackboxes in the Static synthesis.  To do this you just need a module or component declaration for synthesis, so that the tools know the port widths and directions or the RP ports.  You should see messages in the Static synthesis results that the RP is a blackbox.


Then you need synthesize each RM bottom-up with "-iobuf none" switch turned on (see "./Synth/CounCW/CounCW.xst" as an example). This will prevent IO buffer insertion on the RMs, and allow you to stich the RM into the top-level netlist for implementation.  


Also note that if you are targeting 7series devices, the PR flow is now production in Vivado as well.  There is a Tutorial (ug947) and User Guide (ug909) available at

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