cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
orangepeace
Explorer
Explorer
7,958 Views
Registered: ‎11-02-2011

How can I make sure the contents of static logic in different bit files are consistent?

Hi All,

 

   My design is below:

   Part: Virtex-6

   Tool: PlanAhead with Partial Reconfiguration

    There are two reconfigurable partitions in my design RP1 and RP2. Each RP contains two reconfigurable modules.

   That's to say RP1 : RM1a, RM1b;   RP2: RM2a, RM2b  

  I create two configurations: 

    config_1: static logic + RM1a + RM2a

    config_2 : static logic + RM1b + RM2b

 

Questions: 

1. How can I make sure the contents of static logic in each bit file (config_1.bit and config_2.bit) are consistent?

2. If I want to generate a seperate bit file of static logic, how to do it in PlanAhead 14.7?

 

Thanks.

  

0 Kudos
2 Replies
vemulad
Xilinx Employee
Xilinx Employee
7,952 Views
Registered: ‎09-20-2012

Hi,

 

Refer to page-75 "Verifying configurations" of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
vemulad
Xilinx Employee
Xilinx Employee
7,902 Views
Registered: ‎09-20-2012

Hi @orangepeace

 

Did that help?

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos