05-07-2015 02:26 AM
My design is below:
Tool: PlanAhead with Partial Reconfiguration
There are two reconfigurable partitions in my design RP1 and RP2. Each RP contains two reconfigurable modules.
That's to say RP1 : RM1a, RM1b; RP2: RM2a, RM2b
I create two configurations:
config_1: static logic + RM1a + RM2a
config_2 : static logic + RM1b + RM2b
1. How can I make sure the contents of static logic in each bit file (config_1.bit and config_2.bit) are consistent?
2. If I want to generate a seperate bit file of static logic, how to do it in PlanAhead 14.7?
05-07-2015 02:58 AM
Refer to page-75 "Verifying configurations" of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
05-12-2015 03:55 AM
Did that help?