07-23-2019 07:14 AM
I have a Genesys-2 board (Kintex-7) with the system frequency of 200 MHz (Fvco =1000 MHz (MMCM) and Fvco=800 MHz(PLL)). Now I want to create a frequency which higher than 200 MHz. Is it possible?
Please help me. Thank you very much.
07-23-2019 07:23 AM
click on the output tab of the wizard,
and enter what frequency out you want.
07-24-2019 06:42 PM - edited 07-24-2019 06:52 PM
Thank you so much for your answer. I'm so sorry since I questioned without reading carefully the guide.
I found solution for solving my problem. The maximum input frequency of my device is 200 MHz, but I need a higher frequency than 200 MHz. It is 400 MHz.
I used "Allow Overide mode" in MMCM Setting tab to set the output frequency. The actual Frequency that I can obtain at output is diplayed in the "Output Clock" tab. By changing the M, D, O values, I can change the output frequency, as shown in below figure 1. And the actual output frequency is displayed in Fig. 2, 400 MHz, even the input frequency is 200 MHz. I'm not good at this subject so I cannot explain detail, but my tutorial worked well.
07-25-2019 01:26 AM
In older FPGAs, clock modules could only produce output clocks with frequency equal to or lower than their input clock. The Kintex-7 and many other FPGAs from Xilinx have the MMCM clock module. The MMCM can easily and normally generate output clocks with frequencies that are higher (or lower) than the input clock frequency. As drjohnsmith says, simply go to the “Output Clocks” tab of the Clocking Wizard and type the frequency that you want for each output clock.
The “Allow Override Mode” option that you have used is for special and rare situations. I do not recommend using it on a normal basis since it can lead to suboptimal or improper setup of the MMCM.
07-25-2019 02:25 AM - edited 07-25-2019 02:26 AM
Also look carefully into the clocking resources userguide for the FPGA you are using.
You max freq of operation is limited by the frequency the clock buffers inside the FPGA fabric can handle. So even if the MMCM may generate a higher clock frequency, the clock buffers are a limiting factor.