04-10-2017 02:02 AM
In UG909，it is mentioned the "configuration memory" for configuring the logic unit, like CLB.
But I'm still unkown about how the configuration memory architecture work?
Can it configure two configuration frame at the same time, like dual-channel memory?
For example, there are two ICAP to reach that?
Or it is multi-channel?
04-10-2017 03:05 AM
04-10-2017 05:03 AM
@balkris thanks for your anwser.
According to the ug470, there are many modes that user selected and the bus width can be different from 1bit to 32bit.
However, if I have two partial reconfigurable region A and B through a mode and corresponding bus width, internally, the bitstreams can be download to A's configuration memory and B's configuration memory simultaneously? or only one by one? or sometimes A's sometimes B's?
all the condition is whether about the loction of A and B on FPGA chip or not?
04-19-2017 08:50 AM
All configuration of the device, be it the full initial configuration or partial reconfiguration after the device is active, is all managed by a single configuration engine. While this engine has many access ports (ICAP, JTAG, SelectMap, etc.) it will only process one bitstream at a time. So partial reconfiguration of blocks A and B must be performed sequentially.