We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


How much ports the configuration memory has?

Posts: 4
Registered: ‎01-16-2016

How much ports the configuration memory has?

In UG909,it is mentioned the "configuration memory" for configuring the logic unit, like CLB.

But I'm still unkown about how the configuration memory architecture work?

Can it configure two configuration frame at the same time, like dual-channel memory?

For example, there are two ICAP to reach that?

Or it is multi-channel?



Posts: 5,893
Registered: ‎08-01-2008

Re: How much ports the configuration memory has?

check this document

Thanks and Regards
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
Posts: 4
Registered: ‎01-16-2016

Re: How much ports the configuration memory has?

@balkris thanks for your anwser.

According to the ug470, there are many modes that user selected and the bus width can be different from 1bit to 32bit.

However, if I have two partial reconfigurable region A and B through a mode and corresponding bus width, internally, the bitstreams can be download to A's configuration memory and B's configuration memory simultaneously? or only one by one? or sometimes A's sometimes B's? 

all the condition is whether about the loction of A and B on FPGA chip or not? 


Xilinx Employee
Posts: 156
Registered: ‎11-17-2008

Re: How much ports the configuration memory has?

All configuration of the device, be it the full initial configuration or partial reconfiguration after the device is active, is all managed by a single configuration engine.  While this engine has many access ports (ICAP, JTAG, SelectMap, etc.) it will only process one bitstream at a time.  So partial reconfiguration of blocks A and B must be performed sequentially.