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Observer kp1998_
Observer
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Registered: ‎06-11-2019

How to calculate throughput for a hdl code using vivado software

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Hello

I am working on designing pipeline architecture of 1-D DCT and want to know how to calculate throughput for the hdl code using Vivado software.

Thanks

Regards

Neha

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Scholar u4223374
Scholar
359 Views
Registered: ‎04-26-2015

Re: How to calculate throughput for a hdl code using vivado software

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You calculate it based on how you design the HDL, not using Vivado.

 

When you design it, you'll obviously be designing to achieve a specific number of clock cycles per input/output data set. You will need to specify how fast you want it to run and optimize it until you achieve that speed. Once that's done, assuming that you run the block continuously (ie pipeline is always full), your throughput is going to be <clock speed in Hz> / <clock cycles per input/output>.

 

Say your design reads 298 input values at one per cycle (eg. from an AXI Stream), and on the cycle after those are loaded it starts producing 57 output products (also one per cycle). When it finishes this it spends 12 cycles cleaning up internal buffers before it's ready to start again. Your target clock speed is 200MHz. The total number of clock cycles here will be 298 + 57 + 12. Throughput is therefore 200,000,000/367 = about 545K datasets per second.

 

If you pipeline that design so that as soon as it finishes reading the first data set it's ready to make a start on the next one (and outputs happen while it's reading the next one) then total clock cycles is 298, and throughput is about 671K datasets per second.

3 Replies
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Scholar u4223374
Scholar
360 Views
Registered: ‎04-26-2015

Re: How to calculate throughput for a hdl code using vivado software

Jump to solution

You calculate it based on how you design the HDL, not using Vivado.

 

When you design it, you'll obviously be designing to achieve a specific number of clock cycles per input/output data set. You will need to specify how fast you want it to run and optimize it until you achieve that speed. Once that's done, assuming that you run the block continuously (ie pipeline is always full), your throughput is going to be <clock speed in Hz> / <clock cycles per input/output>.

 

Say your design reads 298 input values at one per cycle (eg. from an AXI Stream), and on the cycle after those are loaded it starts producing 57 output products (also one per cycle). When it finishes this it spends 12 cycles cleaning up internal buffers before it's ready to start again. Your target clock speed is 200MHz. The total number of clock cycles here will be 298 + 57 + 12. Throughput is therefore 200,000,000/367 = about 545K datasets per second.

 

If you pipeline that design so that as soon as it finishes reading the first data set it's ready to make a start on the next one (and outputs happen while it's reading the next one) then total clock cycles is 298, and throughput is about 671K datasets per second.

Observer kp1998_
Observer
327 Views
Registered: ‎06-11-2019

Re: How to calculate throughput for a hdl code using vivado software

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Hello how to find target speed in Vivado software. Is it set by default or can be manipulated as per requriement. I am intially giving 8 input values which are then passed through rgister which acts as buffer and then this value is multiplied with DCT coefficient value. So i have to consider for how long it is taking for the input to pass through these registers and multipliers ?? And i have getting only one output value at the end of each clock cycle. This is the scenario i am working in. Please help with this as in how to calculate throughput for this scenario.

Thanks

Regards

Neha

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Scholar markcurry
Scholar
190 Views
Registered: ‎09-16-2009

Re: How to calculate throughput for a hdl code using vivado software

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Neha,

@u4223374 Solution still applies.  You have things backwards.  Target speed, and latencies are NOT outputs from the Vivado tools that are reported - they are input target's you give to the tool.

Your design requirements will dictate the neccessary clock speed, latency, etc.  And then the tool will try and meet those requirements.

If you're asking for a general, hand-wavy "how fast do you think I can make operation XXX operate with FPGA family YYY" well, that's a different (often asked question).  You'll find similar responses in most of those threads - it very much depends on what operation (XXX) you're doing, and what family (YYY) you're targeting - amongst a slew of other variables too.  

Regards,

Mark