cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
rbsexton
Visitor
Visitor
610 Views
Registered: ‎05-09-2019

How to generate a variable frequency clock on Zynq

I've got an application where I need to support variable frequency output.   The application is similar to SPI and runs at ~25MHz and lower.   The timing requirements aren't very strict, but it does have to be negative edge triggered.    I've tried a few different solutions but have yet to find anything satisfactory.  

I have written and deployed IP that does this with a fast side / slow side solution, with the two sides connected by an independent clock FIFO.   The slow side is negative edge triggered.  

My existing code uses a user-adjustable down counter to generate the variable frequency clock.   The synthesis tools don't like this at all.   The synthesis tools identify this as a LUT driving a Clock and complain loudly about hold times.    It triggers the gated clock warnings.    Since the FIFO is the primary consumer of the clock, there is lots of logic in there that I cannot directly control or re-write to add a CE input.

I can't use a BUFGCE with a fast input clock and a slow-toggling  output, because I need a clock with a normal duty cycle for my negative edge logic.  

The other solution I've considered is doing this with an external physical loopback from a IO to a global clock input. 

Or perhaps a fallback solution - choose two internal clocks and let the user choose between a normal clock and a much slower backup speed.  

Does anybody have suggestions as to a legitimate way to solve this that doesn't create a lot of synthesis mess?

0 Kudos
2 Replies
egrigor
Contributor
Contributor
469 Views
Registered: ‎12-11-2007

Do you need to change the frequency within the design or can it be set at compile time?  You can change the output clock frequency of a MMCM via parameters in your code if it constant within a compilation, OR use dynamic reconfiguration of the MMCM if the design needs to alter the frequency.  Refer to the MMCM section of UG572 for further details.

0 Kudos
444 Views
Registered: ‎01-22-2015

@rbsexton 

For these slow speed SPI interfaces, you can do what some call “bit banging” and what is also called an “oversampled interface”.  This method makes it easy to create a variable frequency clock and passes timing analysis “by design”.  Take a look at the following post where I describe the method for use with an SPI interface to flash memory.

https://forums.xilinx.com/t5/FPGA-Configuration/Qspi-flash-memory/m-p/1059383#M15432

Mark

0 Kudos