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Visitor gelineau
Visitor
7,445 Views
Registered: ‎04-02-2015

How to pass a bank placement constraint to Vivado in pre-RTL I/O Pin Planning mode?

At an early stage of the project, I would like to tell Vivado to place the I/O ports within the banks defined by the PCB/Product architect and provided in a CSV file.
As specified in ug899, the 'I/O Bank' field in the CSV file is not read by Vivado during import (it is only an output).
The best solution I found was to create an 'Interface' for each group of ports assigned to a bank and fix one port site within this Interface.
After migrating to an RTL project, Vivado places the ports of a given Interface in the bank corresponding to the fixed port. That is an acceptable workaround.
But it should be better if I can just tell Vivado to place a group of ports in a given bank without assigning sites beforehand.
Is it possible?

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Observer chris1220
Observer
126 Views
Registered: ‎09-19-2013

Re: How to pass a bank placement constraint to Vivado in pre-RTL I/O Pin Planning mode?

With a Vivado .xdc constraints file, the following is the syntax:

set_property IO_BANK BankNumber [get_ports PortName]

-Chris

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