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Explorer
Explorer
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Registered: ‎08-15-2014

How to report Combinatorial Loop path?

HI,

I receive below combinatorial loop warning, 

May I know how to report exact path/hierachy of combinatorial loop?

I want to know which code cause this combinatorial loo?

 

WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolutio n is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS pr operty on a net in the loop. The cells in the loop are: stop_clock_checker_inst_2/assert_stop_inferred_i_1.
10682 WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolutio n is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS pr operty on a net in the loop. The cells in the loop are: stop_clock_checker_inst_2/assert_stop_inferred_i_2.
10683 WARNING: [DRC PDRC-153] Gated clock check: Net _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[0]_i_3_n_0 is a gated clock net sourced by a combinational pin _RPP_COMPILER_ RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[0]_i_3/O, cell _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[0]_i_3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
10684 WARNING: [DRC PDRC-153] Gated clock check: Net _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[1]_i_3_n_0 is a gated clock net sourced by a combinational pin _RPP_COMPILER_ RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[1]_i_3/O, cell _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[1]_i_3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
10685 WARNING: [DRC PDRC-153] Gated clock check: Net _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[2]_i_3_n_0 is a gated clock net sourced by a combinational pin _RPP_COMPILER_ RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[2]_i_3/O, cell _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[2]_i_3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
10686 WARNING: [DRC PDRC-153] Gated clock check: Net _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[3]_i_3_n_0 is a gated clock net sourced by a combinational pin _RPP_COMPILER_ RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[3]_i_3/O, cell _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[3]_i_3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
10687 WARNING: [DRC PDRC-153] Gated clock check: Net _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[4]_i_3_n_0 is a gated clock net sourced by a combinational pin _RPP_COMPILER_ RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[4]_i_3/O, cell _RPP_COMPILER_RESERVED_NAME_RPP_TRIGGER_COUNTER_NET_2/count[4]_i_3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.

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Teacher
Teacher
359 Views
Registered: ‎07-09-2009

Re: How to report Combinatorial Loop path?

the way to easily look at this, is to notice , its complaining abut your signal "count" , bits 0 to 4

You also have notes there about gated clock on count,


so can you post as an attachment your code, and your constraints
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