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crazywolf
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How to trigger the partial reconfiguration

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Hi, everyone

         I have tried to do the partial reconfiguration with my KCU105 board.

         I have read the lab 4 in the ug947, and could program the child bitstream successfully. However i want to download the partial reconfiguration bitstream with the code ,but not by clicking the button in vivado when i need it. In other words,i want complete the partial reconfiguration with the code or command.

         Please tell me that is there any method can i trigger the partial reconfiguration automaticly with the code? Is there any pdf of the guide can help me with this problem?

 

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davidd
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Registered: ‎11-17-2008

@crazywolf,

 

First, partial bitstreams are just data files.  You just need to store them in a format that will shift properly into the ICAP when retrieved.  For example, write_cfgmem -format BIN -interface SMAPx32 -disablebitswap ...  I'm not a memory interface expert, but perhaps someone can chime in to suggest different ways to package this up for easily pushing this image into DDR4 for AXI-based retrieval.  I do have someone building a sample PRC design that uses MicroBlaze to transfer partial bitstreams from QSPI to DDR4 but it's not complete yet, and even then, it's just one method.

 

Second, yes, you don't need the hwicap if you've directly instantiated the ICAP.  The hwicap IP is a wrapper around the ICAP in order to access it over AXI4-Lite, as you can see in PG134.  Even though the PR Controller pulls in data over AXI, it directly accesses the ICAP so the wrapper layer is unnecessary (although you may need to arbitrate access if some other part of the design needs to use it).

 

thanks,

david.

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syedz
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@crazywolf,

 

when you use project mode, all the equivalent commands will be displayed in Vivado TCL console which can be used in your script. Also refer to the User guide on PR:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug909-vivado-partial-reconfiguration.pdf

 

--Syed

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crazywolf
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     Thank you for helping me. But could you please tell me which chapter can i find the method to trigger the partial reconfiguration in ug909?

     I have downloaded the ug909 before. In the CH.8, it tell about the configuration modes. Is it the right chapter which can help me?

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crazywolf
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Thank you for helping me. But could you please tell me which chapter can i find the method to trigger the partial reconfiguration in ug909?
I have downloaded the ug909 before. In the CH.8, it tell about the configuration modes. Is it the right chapter which can help me?
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crazywolf
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@syedz,

     Thank you for helping me. But could you please tell me which chapter can i find the method to trigger the partial reconfiguration in ug909?

     I have downloaded the ug909 before. In the CH.8, it tell about the configuration modes. Is it the right chapter which can help me?

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davidd
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@crazywolf,

 

How you trigger partial reconfiguration is up to you as the designer.  PR occurs when you deliver a partial bitstream to a configuration port, so the triggering is part of your design and must be set up to occur when you need it to.  Ask yourself these questions:

  • When is a new function needed?
  • How will I deliver the partial bitstream to the configuration port?
  • Which configuration port will I use?
  • Where are the partial bitstreams stored?

All these and more are elements to triggering.  Once those are answered, these are the next questions:

  • What is currently happening in the PR region?  Do I need to wait or flush activity before sending a new bitstream?
  • How will I decouple the partition interface to ensure this changing logic doesn't negatively affect the rest of the design?
  • What other synchronization events need to occur when PR completes?

Xilinx offers examples and IP to help answer these questions, or you are certainly free to design your own solution.  The PR Controller IP is a manager that helps with hardware or software triggering, arbitration, and bitstream delivery over AXI.  The PR Decoupler IP will help you easily isolate a reconfiguring region.  Any other handshaking or pre- or post- reconfiguration events are up to you to manage as part of your system-level design.

 

But it still all hinges on sending a partial bitstream to a configuration port.  In these simple labs in UG947, we focus mainly on the implementation design flow.  Labs 1-4 just send partials over JTAG from the Vivado Hardware Manager, but clearly that is really just for lab and education environments.  Labs 5-6 show the PR Controller sending bitstreams from local flash to the ICAP.  Other examples like XAPP1231 and XAPP1099 show management and delivery over the Zynq PS and via MicroBlaze, respectively.  Or you can use external ports that are persisted for configuration use and are connected to memory storage elements.

 

Chapter 8 of UG909 is the right place for the nuts and bolts of how PR configuration can occur, but you need to apply this to your design as you see fit.

 

thanks,

david.

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crazywolf
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@davidd,

      Thank you so much for these useful answers. But i still have some questions.

      I want to send the partial bitstreams from local flash or DDR3 to the ICAP exactly. But i still can not find a effective way to write the right code to deliver the partial bitstreams to the ICAP with Verilog.

      I have noticed the PR Controller IP core and tried to use it follow the ug193 and ug947. But,there are some words in the Lab6 from ug947. It says The KCU105 development board is not supported, as the boot flash on this board is a QSPI device. QSPI and sync-mode BPI configuration schemes are not supported for Partial Reconfiguration. However i only have the KCU105 development board to test the function. Is that means the PR Controller cannot be used in the KCU105 development or just the example in the Lab6 cannot be used?

      Now,i try to find some ways from the chapter 8 of the UG909 and i notice the Table 8-1. Is it means i cannot use the SPI to deliver the partial bitstreams with the KCU105 board? Because i find a method in XAPP1257. It seems can help me. But,it use the SPI to complete the function. Please tell me if the XAPP1257 can really figure out my problem? Or i just find the wrong way.

 

thanks,

crazywolf.

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davidd
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@crazywolf

 

The comments on the KCU105 for the PR Controller are to remind users that not every configuration mode is supported for PR in that architecture, so unfortunately the QSPI available on that board cannot be used to deliver partial bitstreams.  (It doesn't help you now, but UltraScale+ does not have this limitation.)  Only the example in Lab 6 cannot be used given that it was created for sync-mode BPI for the VCU108.  Any other local flash that you can access via AXI (without the use of the STARTUP module)  would be fine, so the on-board DDR4 on the KCU105 may be the answer.  I do not have an example design that takes this approach though.

 

thanks,

david.

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crazywolf
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@davidd,

Thank you for helping me,davidd.

Do you mean the PR Controller can be used on the KCU105 board with the bitstreams stored in the on-board DDR4? If that's so. I have some questions about that.

How can i store and deliver the bitstreams in the on-board DDR4? Is there any guide can help me? Can i find some message from the DDR4 Controller Ip Core User Guide?

Is  DDR4 the only way to store and deliver the bitstreams ? If i can use the other local flash, which flash can be supposed on the KCU105 board? And is there any guide can help me to store and deliver the bitstreams with that flash?

 

thanks,

crazywolf.

 

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crazywolf
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@davidd,

Hi,davidd. I have a idea and find some guide to solve my problems.

It seems i can use the HWICAP IP Core(PG134) to deliver the partial bitstreams from the local flash or DDR4 to ICAP,and i can decide when the partial bitstreams can be delivered with the HWICAP. In the other word, it seems can figure out the trigger problem i asked before if i can store the partial bitstreams in the flash or DDR4 successfully and complete the logic configuration of HWICAP IP Core.

Please tell me if i find the right way. If that's so. I can continue my research. It's so important for me.

 

thanks,

crazywolf.

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davidd
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@crazywolf,

 

There are many ways to deliver partial bitstreams to the ICAP, and yes the hw-icap is certainly a good one.  It still just comes down to shifting bitstream data into the ICAP when you're ready to reconfigure.  If you using the PR Controller IP, it just needs to see an addressable space on an AXI bus and then also have the ICAP connected -- see UG947 for examples.  If using something like MicroBlaze, the same sort of thing applies, but now you manage the addressing request -- see XAPP1099 for an example.  You can pull sections of the design directly from these examples or build your own.  There is no specific "right way" to do this, just the "right way for you" depending on all your requirements.

 

thanks,

david.

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crazywolf
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@davidd,

Thank you for your answer,davidd.

Since i only have the KCU105 board. Now i prepare to store the partial bitstreams in the DDR4 and deliver it to the ICAP through the hw-icap to finish my design. It is a viable idea,isn't it?

Now i'm learning how to use the hw-icap through the PG134. Then i will figure out how to store and read back the partial bitstreams in the DDR4. And i will read the XAPP1099 you recommended to manage the addressing request. I will keep this way if my idea is viable.

 

thanks,

crazywolf.

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crazywolf
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@davidd,

Hi,davidd. There are still some questions confused me now.

Did you mean that if i use the PR Controller IP, i can complete my design with PR Controller IP,DDR4 and hw-icap modules? In the other word, it means the PR Controller IP can deliver the partial bitstreams from DDR4 to hw-icap through the axi4 line and then hw-icap can deliver the bitstreams to ICAP to complete the partial reconfiguration?And it can realize on the KUC105 board?

 

thanks,

crazywolf.

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davidd
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@crazywolf,

 

If you're going to be using the PR Controller IP, hopefully you've reviewed PG193.  It states:

"The Partial Reconfiguration Controller core fetches bitstream data from an AXI4 bus and, as a result, is not directly tied to any particular storage device. This allows the controller to access bitstreams no matter where they are stored, as long as a compatible AXI4 interface is available. The Vivado IP catalog contains several such blocks of IP, such as the AXI External Memory Controller (axi_emc), and the Memory Interface Generator (MIG).

Note: The STARTUP primitive does not support loading of partial bitstreams. IP, such as AXI SPI or AXI EMC should not be configured to use the STARTUP primitive to clock or deliver partial bitstreams from external flash." This note is for UltraScale and older devices.

 

In the example in UG947 that targets UltraScale (lab 6), we connect the PRC to the ICAP directly as it has the interface ports explicitly declared.  The HWICAP is for more general AXI access, such as from a MicroBlaze.  In this example you could replace the AXI-EMC with a DDR4 MIG core.  I have not personally built this example (there are tons of combinations I have never built) but I've seen similar.  One of the benefits of a standard interface structure like AXI is that you can easily stitch together peripherals like this.  You'd need to work out the address mapping on your own to fit your design needs, and you'll need to reference MIG and/or KCU105 documentation for guidance on how to program the DDR4 memory.  But that lab example shows how we build a flash image that stacks up the full and partial bitstreams, and how the different parts of the PR design are put together.  It's up to you to customize it to meet the goals of your project.

 

thanks,

david.

crazywolf
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@davidd,

Thanks for your very useful advice,davidd.

I knew that the PR Controller IP  fetches bitstream data from an AXI4 bus which connected to the on-board DDR4.

But there are two questions still confuse me.

First, how can i store the bitstreams in the DDR4? In the PG150 it seems only tell me how to write and read data through DDR4 MIG Core in Verilog HDL. And i didn't find a method to store the bitstreams in DDR4 either in PG150 or community.

Secondly, if the HWICAP is for more general AXI access, such as from a MicroBlaze. Does it means if i use the PR Controller IP in my design,i will complete my project without the HWICAP because of the similar function they do? In other words, after getting the bitstreams from AXI4 bus PR Controller IP can finish the partial reconfiguration without other modules?

 

thanks,

crazywolf.

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davidd
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@crazywolf,

 

First, partial bitstreams are just data files.  You just need to store them in a format that will shift properly into the ICAP when retrieved.  For example, write_cfgmem -format BIN -interface SMAPx32 -disablebitswap ...  I'm not a memory interface expert, but perhaps someone can chime in to suggest different ways to package this up for easily pushing this image into DDR4 for AXI-based retrieval.  I do have someone building a sample PRC design that uses MicroBlaze to transfer partial bitstreams from QSPI to DDR4 but it's not complete yet, and even then, it's just one method.

 

Second, yes, you don't need the hwicap if you've directly instantiated the ICAP.  The hwicap IP is a wrapper around the ICAP in order to access it over AXI4-Lite, as you can see in PG134.  Even though the PR Controller pulls in data over AXI, it directly accesses the ICAP so the wrapper layer is unnecessary (although you may need to arbitrate access if some other part of the design needs to use it).

 

thanks,

david.

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jhardy1
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Hi David,

  1. Is the sample design you mentioned that uses MicroBlaze to transfer partial bitstreams from QSPI to DDR4 complete and publicly available?
  2. I'm confused about Lab #6 in UG947. When I open the corresponding example design I see that it includes the STARTUPE3 primitive and that the AXI EMC module is connected directly to the Partial Reconfiguration Controller. Furthermore, in a post above you mention that "Lab 6 ... was created for sync-mode BPI for the VCU108." However UG909 states that sync-mode BPI is not supported for partial reconfiguration. Therefore, it seems like this design should not work for partial reconfiguration, but it obviously must work because it is part of the tutorial. Can you help clear up my confusion?

Thank you,

Josh

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davidd
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@jhardy1,

1. The sample design I mentioned is Lab 7 in UG947.  This example targets UltraScale+ only, as prior architectures did not support loading partial images over QSPI.

2. Ah, that's just a typo from me in this thread.  As you note, the different supported configuration modes are listed in table 11 in UG909.  Note there are differences per family -- more modes are supported in newer architectures.  And yes, the lab does work.

Hopefully you've already found this out -- I didn't see your reply over the holiday break.

thanks,

david.

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