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Visitor
Visitor
13,835 Views
Registered: ‎01-19-2009

How to use a general I/O pin as a dedicated clock pin.

Hi, everyone...

 

Accidentally, I assign a general I/O pin of SPARTAN-3 as system clk.

And I code as following, bit I have an error message.

Of cause, the error message is that A clock IOB / clock component is not placed at an optimal clock IOB.

As far as I know, I can remove this error message using component ibuf and bufg as following.

 

I don't understand why the error message is occurred...

 

entity test_clk is
    port
    (
       clk_in : in std_logic;
       data : out std_logic
    );
end test_clk;

 

architecture Behavioral of test_clk is
    signal clk0 : std_logic;
 
    component ibuf
    port
    (
         i : in std_logic;
        o : out std_logic
    );
    end component;
  
    component bufg
    port
    (
        i : in std_logic;
       o : out std_logic
    );
    end component;

begin
 
   U0 : ibuf
   port map
   (
      i=>clk_in,
      o=>clk0
   );
 
   U1 : bufg
   port map
   (
      i=>clk0,
     o=>clk
   );

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2 Replies
Explorer
Explorer
13,830 Views
Registered: ‎04-06-2009

Read the Global Clock Network in the Datasheet.

Spartan-3 devices have Global Clock inputs called GCLK0 - GCLKn. These inputs provide access to a low-capacitance, low-skew network that is well-suited to

carrying high-frequency signals.

 

Also read the IOB part in the Datasheet. Where as in IOB, there are three main signal paths within the IOB: the output path, input path, and 3-state path. Each path has its own pair of storage elements that can act as either registers or latches.

 

When in your code you are using a signal inside a process with " ' Event ", it consider it as a clock. In a digital circuit if your Clk is unstable (because of propogation delays, path delays etc....) then your circuit is more prone to eronious behaviour. So it is always advisible not only to use Global Clock pins for Clk inputs but also to make sure that your clock signal is routed through the Global Clock Network.. 

 

Shantanu

Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335
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Voyager
Voyager
13,818 Views
Registered: ‎08-30-2007

Are you getting an error message or a warning?  It is legal to use a general purpose IO pin

to bring in a global clock but it is very sub-optimal.

 

Since the GP-IO pin does not have a dedicated path to a clock buffer, it has to use general

fabric routing which can cause excessive delay and possibly duty cycle distortion.  You may

not care about either of these, but if you're trying to synchronously get data from an external

source, you may have some difficulties with setup/hold time.

 

You can add MAXDELAY type constraints in your ucf file to try to force an acceptable delay

on the clock signal, but the FPGA can only do so much since it has to use fabric to route the

pad to the global clock.

 

John Providenza

 

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