Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎02-10-2015

How to write bitstream to ICAP in partial reconfiguration?


I want to use FPC (XAPP 883) with my own software and transfer the bitstream by LAN.

What is the write flow to fpga? (SOC, SYNC,Data, EOC)

should I remove the header of bitstream?

How does PR Loader software extract the bitstream?



0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎02-20-2008



generally speaking the flow is pretty simple. You need to make sure that the "real" PR bit-stream ends at the ICAP-module correctly.

The SOC/ EOC-pattern in the application-note are just arbitrary pattern that were used in the example-design for a bit off control what is happening. The ICAP-module itself does not care about it.

Where it starts to get interesting is when the real bit-stream comes along with the SYNC-pattern and the alignment-word. These need to be located at the right boundaries. If you are going for an 8 Bit Interface at the ICAP you don't need to worry, however if you go for 16 or 32 Bits than you need to make sure that the SYNC- and alignment-pattern are properly distributed over the 16/32 Bits.

I seem to remember that the example-design didn't like it when the PR-bitstream came one or three bytes short (in my case some additional data before the initial FF FF ...) and hence the word-boundaries on the ICAP were missed. But a lot of dust on my memory on that topic...


The real PR-bitstream needs to be fully loaded into the ICAP-module, otherwise you will not get a correct reconfiguration.


Hope that helps,



0 Kudos