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gonen
Visitor
Visitor
10,990 Views
Registered: ‎12-11-2013

I need a guide for RPM creation for ISE 14.7

Trying to loop-generate 32 FFT IP cores with some surrounding logic - I want to create one RPM and have the synthesis replicate is as-is:

(1) maintain relative placment

(2) maintain timing/routing.

(3) deny other user-logic implementation withing macro area.

(4) replicate RPM 32 times.

 

All guides I found are related to old software.

 

Is there a better alternative? Hard Macro?

 

Please advice.

 

Thnaks,

gonen.

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13 Replies
vemulad
Xilinx Employee
Xilinx Employee
10,974 Views
Registered: ‎09-20-2012

Hi,

For RPM related constraints refer to page-221 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/cgd.pdf

Thanks,
Deepika.

Thanks,
Deepika.
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gonen
Visitor
Visitor
10,964 Views
Registered: ‎12-11-2013

Thanks a lot Deepika,

 

Is this applicable for ISE tool (the link is for VIVADO)?

 

Gonen.

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gonen
Visitor
Visitor
10,961 Views
Registered: ‎12-11-2013

The linked PDF has only 170 pages?
Where is page-221?
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vemulad
Xilinx Employee
Xilinx Employee
10,958 Views
Registered: ‎09-20-2012

Hi,

 

Sorry, that was a wrong link. I now updated my first post with correct link.

 

Thanks,

Deepika.

Thanks,
Deepika.
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gonen
Visitor
Visitor
10,952 Views
Registered: ‎12-11-2013

Thanks a lot - Link is OK now.

 

I've read this section before but what I'm looking for is a "walkthrough" guide and/or tutorial on how to:

(1) create the RPM in the first place from successful synthesis results

(2) how to use this new RPM at the new design (generate-loop of 32 RPMs).

 

Maybe I'm missing something ?

 

Something like:

(1) implement one FFT successfully

(2) Use some tool/script/method to export results to RPM (netlist? ucf? format? where to place it?)

(3) Use another method to instantiate the new FFT RPM at the top design.

 

Thanks a lot,

 

Gonen.

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balkris
Xilinx Employee
Xilinx Employee
10,937 Views
Registered: ‎08-01-2008

Here are some examples of how to get more imformation about the RAM in a design.

Getting a list of all BRAMS:

set my_rams [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* }]

Counting the length of the list:

llength $my_rams

Reporting out the properties of all the brams:

foreach test $my_rams {report_property -all [get_cells $test]}

Creating a set of brams with a specific attribute:

set no_doa_reg [get_cells -hierarchical -filter { PRIMITIVE_TYPE == BMEM.bram.RAMB36E1 && DOA_REG == "FALSE" }]

Creating the specific sets based on properties and then getting the list length may be more of what you are interested in:

show_objects -name find_3 [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ DMEM.*.* } ]

To get the width and the height, you could go from the RAM cells to the sites and use the Site properties, or maybe even another step from Sites to Tiles:

set site [get_sites -of_objects [get_cells <switches>]]
report_property -all $site
set tile [get_tiles -of_objects $site]
report_property -all $tile

From the site and tile properties you can get the X and Y RPM and regular coordinates as properties directly.

To get all of the rams in the open design:

all_rams

To see the carry chain sizes:

report_carry_chains -max_chains 100

To get distributed memory:

get_cells -hierarchical -filter { PRIMITIVE_GROUP == DMEM }
get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ DMEM.*.* }

To get block memory:

get_cells -hierarchical -filter { PRIMITIVE_GROUP == BMEM }
get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.*.* }

Parent property can be used to get the instance name:

PARENT cell true true cpuEngine/cpu_dbg_dat_i/buffer_fifo

Parent filter can be used to get all of the children that make that instance:

get_cells -hierarchical filter {PARENT == cpuEngine/cpu_dbg_dat_i/buffer_fifo}

To get the type of memory (or PRIMITIVE_TYPE):

get_property REF_NAME [get_cells <switches>]

Check DO*_REG is TRUE to see if an output is registered:

get_property DOA_REG [get_cells <bram_switches>]
Thanks and Regards
Balkrishan
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gonen
Visitor
Visitor
10,934 Views
Registered: ‎12-11-2013

Thanks a lot for the elaborate response!

 

Still, I find it very hard to believe that such a well-established procedure like RPM creation does not have a proper GUI walkthrough or a proper white-paper.

 

What you're suggesting is very very "manual" and seems like a very tedious work which also requires very good understanding of the RPM content.

 

For complex blox with IP cores for example this seems impractical.

 

So - any WIKI? known general purpose procedure for RPM creation?

 

Thanks,

Gonen

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ashishd
Xilinx Employee
Xilinx Employee
10,930 Views
Registered: ‎02-14-2014

Hello,

For general procedure of RPM creation, I think it will be better to go through below answer record. The design and constraint file is also attached with it. You will get basic idea after following this AR
http://www.xilinx.com/support/answers/51602.html

For additional information, there is a good white paper to refer
http://www.xilinx.com/support/documentation/white_papers/wp329.pdf
Regards,
Ashish
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gonen
Visitor
Visitor
10,926 Views
Registered: ‎12-11-2013

Thanks - will look into it...

 

One more thing - are hard-macroes an alternative?

 

I managed to go through all steps in this guide:

http://wiki.eng.iastate.edu/reconfigurable-computing-wiki/index.php/Creating_Hard_Macros

 

But got lost at the last section:

Caution: Constant signals (VCC/GND) should not be included in a hard macro. This will produce errors when building the instantiating project. Constant signals can be generated using LUTs instead.

 How can I replace the GLOBAL_LOGIC0 & GLOBAL_LOGIC1 with "LUT"?

 

Is this the way to go?

 

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gonen
Visitor
Visitor
9,490 Views
Registered: ‎12-11-2013


ashishd wrote:
Hello,

For general procedure of RPM creation, I think it will be better to go through below answer record. The design and constraint file is also attached with it. You will get basic idea after following this AR
http://www.xilinx.com/support/answers/51602.html

For additional information, there is a good white paper to refer
http://www.xilinx.com/support/documentation/white_papers/wp329.pdf

 

 

 

 

 

 

 

 

 

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gonen
Visitor
Visitor
9,486 Views
Registered: ‎12-11-2013

Found this VERY old article on RPM:
http://www.xilinx.com/support/documentation/application_notes/xapp422.pdf

Is it still supported?
What is the latest alternative?
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vemulad
Xilinx Employee
Xilinx Employee
9,471 Views
Registered: ‎09-20-2012

Hi,

 

Refer to page-85 "Directed routing" in http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/cgd.pdf

 

Hope this helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
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gonen
Visitor
Visitor
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Registered: ‎12-11-2013

Thanks Deepika,

 

I'm familiar with this doc,

 

See here:

http://www.xilinx.com/support/answers/35556.html

Note: DIRT constraints are best used to constrain justa few critical nets. If overused they interfere with the router's ability to rip-up and re-route to accommodate other nets. There is also a problem associated with DIRT constraints due to the fact that the placer is not routing aware. The placer may place a component into a location where a routing path is blocked by a DIRT route. This most frequently occurs for Slice FFs using the direct inputs (AX, BX, CX, DX) where the input routing path is blocked by a DIRT route that uses a switchbox bounce off the pin used to access the direct input. The likelihood of this occurring goes up with the number of DIRT routes. This can be avoided with either PROHIBIT constraints or a combination of pack constraints that prevent the problem FF BEL site from being used.

 

Two issues arrise using DIRT here:

(1) As I'm trying to "lock" a rather large unit (Xilinx FFT + some wrapper logic), theres are more then 1000 components to constrain which is problematic as stated above.

(2) Many of the block components listed by FPGA editor does not support location constraints and there is no way of knowing which. Thus, I have to manually try to extrat DIRT from each and every component. Very tedious.
I guess I can write a script somehow.

 

Assuming I succeed, hoe do I continue from this point onwards - generating 32 instances of the FFT RPM?

How do I make sure the NCF has all related DIRT instructions?

What is the "work-flow' in this case.

 

Again, Due to the above, I'm not sure DIRT is the answer...

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