12-13-2014 02:22 PM
Trying to loop-generate 32 FFT IP cores with some surrounding logic - I want to create one RPM and have the synthesis replicate is as-is:
(1) maintain relative placment
(2) maintain timing/routing.
(3) deny other user-logic implementation withing macro area.
(4) replicate RPM 32 times.
All guides I found are related to old software.
Is there a better alternative? Hard Macro?
12-13-2014 11:45 PM - edited 12-14-2014 08:02 AM
For RPM related constraints refer to page-221 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/cgd.pdf
12-14-2014 08:03 AM
Sorry, that was a wrong link. I now updated my first post with correct link.
12-14-2014 08:36 AM
Thanks a lot - Link is OK now.
I've read this section before but what I'm looking for is a "walkthrough" guide and/or tutorial on how to:
(1) create the RPM in the first place from successful synthesis results
(2) how to use this new RPM at the new design (generate-loop of 32 RPMs).
Maybe I'm missing something ?
(1) implement one FFT successfully
(2) Use some tool/script/method to export results to RPM (netlist? ucf? format? where to place it?)
(3) Use another method to instantiate the new FFT RPM at the top design.
Thanks a lot,
12-14-2014 09:59 AM
12-14-2014 10:37 AM
Thanks a lot for the elaborate response!
Still, I find it very hard to believe that such a well-established procedure like RPM creation does not have a proper GUI walkthrough or a proper white-paper.
What you're suggesting is very very "manual" and seems like a very tedious work which also requires very good understanding of the RPM content.
For complex blox with IP cores for example this seems impractical.
So - any WIKI? known general purpose procedure for RPM creation?
12-14-2014 10:51 AM
12-14-2014 11:13 AM
Thanks - will look into it...
One more thing - are hard-macroes an alternative?
I managed to go through all steps in this guide:
But got lost at the last section:
Caution: Constant signals (VCC/GND) should not be included in a hard macro. This will produce errors when building the instantiating project. Constant signals can be generated using LUTs instead.
How can I replace the GLOBAL_LOGIC0 & GLOBAL_LOGIC1 with "LUT"?
Is this the way to go?
12-14-2014 11:28 AM
For general procedure of RPM creation, I think it will be better to go through below answer record. The design and constraint file is also attached with it. You will get basic idea after following this AR
For additional information, there is a good white paper to refer
ashishd - thanks,
This are indeed very simple example and this is not my case.
The xilinx FFT + my logic has handreds of components & some components are not supported by RLOC (this is why "Directed routing constraind" fails I guess).
It is impractical for me to manually write these RLOC constraints - I want to auto-extract them from former implementation.
I can't also place it at VHDL as it involves many files and has thousands of code lines.
These are very old examples and will work only with very simple, self-generated designs.
12-15-2014 04:07 AM
Refer to page-85 "Directed routing" in http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/cgd.pdf
Hope this helps.
12-15-2014 04:59 AM
I'm familiar with this doc,
Note: DIRT constraints are best used to constrain justa few critical nets. If overused they interfere with the router's ability to rip-up and re-route to accommodate other nets. There is also a problem associated with DIRT constraints due to the fact that the placer is not routing aware. The placer may place a component into a location where a routing path is blocked by a DIRT route. This most frequently occurs for Slice FFs using the direct inputs (AX, BX, CX, DX) where the input routing path is blocked by a DIRT route that uses a switchbox bounce off the pin used to access the direct input. The likelihood of this occurring goes up with the number of DIRT routes. This can be avoided with either PROHIBIT constraints or a combination of pack constraints that prevent the problem FF BEL site from being used.
Two issues arrise using DIRT here:
(1) As I'm trying to "lock" a rather large unit (Xilinx FFT + some wrapper logic), theres are more then 1000 components to constrain which is problematic as stated above.
(2) Many of the block components listed by FPGA editor does not support location constraints and there is no way of knowing which. Thus, I have to manually try to extrat DIRT from each and every component. Very tedious.
I guess I can write a script somehow.
Assuming I succeed, hoe do I continue from this point onwards - generating 32 instances of the FFT RPM?
How do I make sure the NCF has all related DIRT instructions?
What is the "work-flow' in this case.
Again, Due to the above, I'm not sure DIRT is the answer...