cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Participant
Participant
192 Views
Registered: ‎03-02-2017

ICAP for PR FPGA programming

Hi,

 

I am currently working on a design where only one cell content ever changes. I would like to program the FPGA with the static part and only generate a new bitstream for this one particular cell (the interface netlist for this cell is also fixed) and then program the FPGA through ICAP (from UltraScale processor). I have seen some PR tutorials but in every design both the static and the variable bitstream were generated at the same time, but I want to generate the static bitstream only once. Is this even possible with ICAP and if yes, is there some tutorial about this?

Thanks!

Capture.PNG
0 Kudos
1 Reply
Highlighted
Moderator
Moderator
89 Views
Registered: ‎11-04-2010

The partial bitstream can be generated without full design bitstream with the option -cell in write_bitstream command:

Ex: write_bitstream -cell [get_cells rm_cell_name] XX.bit

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos