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Adventurer
Adventurer
667 Views
Registered: ‎09-06-2016

ILA triggering on an invisible signal, and it undersamples the clock displayed.

See the attached display.  Note that the ILA triggers, but does not display the signal it triggered on.  It seems to require almost DC to see the trigger.  The clock to the ILA probe block is 402 MHz.

The clock being displayed is supposed to be 100 MHz, but is obviously being sampled wrong.

Is there anything the ILA is useful for in testing high speed designs?

Debugging with these tools has hit the extreme pain level.

ila_probe-2.jpg
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Moderator
Moderator
546 Views
Registered: ‎11-09-2015

HI @srdatucsd 

I am not exactly sure of what is the behaviour of having the signals =X (don't care). What is the behaviour is you remove all the other comparator and keep only the one on c2a_valid?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Scholar
Scholar
537 Views
Registered: ‎08-07-2014

@srdatucsd ,

The clock being displayed is supposed to be 100 MHz, but is obviously being sampled wrong.

Is there anything the ILA is useful for in testing high speed designs?

Are you trying to probe a clock signal or I should better say a periodically toggling signal using ILA?

From the SS it looks like clock signal, 100 MHz, is used as one of the debug signals (but I may be wrong). If this is so, then this is not what is meant for. If not just ignore what I have written below.

My experience with ILA cores show that they work best when used for non-clock type of signals. You connect only ONE toggling signal to the ILA, i.e. your clock signal to the ILA core clock pin. Also all other signals whether trigger or debug MUST belong to the domain of the clock signal connected. Anything else you do might show unstable/wrong behavior of the probed signals.

Debugging with these tools has hit the extreme pain level.

Yes. I only get in ILAs when a bug shows up after design Impl, such that it went undetected during functional verification or which cannot reproduced in simulation.

------------FPGA enthusiast------------
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Adventurer
Adventurer
516 Views
Registered: ‎09-06-2016

It makes no difference.

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Teacher
Teacher
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Registered: ‎07-09-2009

regarding the IL, and sampling a periodic signal, like a clock,

Your sampling at 402 MHz, and the periodic signal is 100 Mhz,
so you would expect just over two sampels high , just over two samples low.

But the ILA core, can only sample integer times, so sometimes it will get 3 high , some times 2 high, and the same for low,

Ona scope, you expect atleast 10:1 sampling to see anything approximately symmetrical.

Add to that, is it a 100 Mhz clock your sampling ? If so is that on a global **bleep** route, by putting it into the ILA logic input , its going to have to come off the global route, who knows what that does to the set up / hold.

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Adventurer
Adventurer
491 Views
Registered: ‎09-06-2016

ila_probe-1.jpg

Explain to me how if I take 4 (2.5ns) samples every 10ns (5 hi, 5 lo period at 100 MHz) that I can see 3 highs that are not continuous or 3 lows likewise.  To clarify, if I zoom in to a 10ns interval, I may see 2-4 clock cycles of the 100 MHz.

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Teacher
Teacher
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Registered: ‎07-09-2009

First up, 

   looking at your numbers, 100 MHz , is a period of 10 ns,

        at 2.5 ns sample , ideal you would get two high and two low.

 

 

Your doing a none integer sampling of a signal,
this is going to be by definition asynchronous.

As your over sample rate is so low, then you have to do the statistics, but I recon if you sampled for say a few seconds, then you would start to see the average number of high and low being the same.
I'd bet you are also seeing a fair amount of metastability and set up / hold issues.

This is all quiet usual with an asynchronous / synchronous sampling approach.

Logic analysers by definition are best at synchronous signals,
you need a scope for asynchronous

Suggestions if you do want to check the frequency of the 100 MHz, using the ILA,

you can do something like a counter, on the clock you wish to check. Grab the count value on a regular basis based upon the reference clock, a bit of clock crossing, and the count value is going to be determinantal.

If you want to look at data .on a different clock to the ILA,
then you can dump the data into a fifo on the clock you data is on, and then read it out at the clock of the ILA. Triggering data capture etc needs to be on the input clock to the fifo,




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Scholar
Scholar
426 Views
Registered: ‎08-01-2012

@srdatucsd you sample clock period is not 2.5 ns, it is 2.487 ns . You cannot round to nearest here, and you'll get the result @drjohnsmith talks about.

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Adventurer
Adventurer
368 Views
Registered: ‎09-06-2016

Thanks for the explanation and the counter/fifo suggestions.  I can see now that the primary cultpret is the metastability due to the asynchronous sampling.  I did not think about how that could turn a 100 MHz clock into a 400 MHz trace display, but this is the best explanation I've heard.  As you say, it should average out over a long time.

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