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Visitor
Visitor
10,517 Views
Registered: ‎04-27-2010

Implementation problems with planAhead

Hello everyone,

I'm building a project that includes a processor, a DDR2 and a hardware TEMAC. It works when I implement the project on XPS 11.5 but when I import ngc files and the ucf file into planAhead 11.5 I have several errors.

Firstly, when I run DRC : Design has more than one IDelay controllers unloced (for example DDR2_SDRAM/gen_no_iodelay_grp.gen_instantiate_idelayctrls[2].idelayctrl0 and DDR2_SDRAM/gen_no_iodelay_grp.gen_instantiate_idelayctrls[1].idelayctrl0). At most one of them can be unloced.

Then I tried to implement the project, even if I have an error, and I have errors like this :
ERROR:Pack:2780 - The register
   "Hard_Ethernet_MAC/Hard_Ethernet_MAC/V5HARD_SYS.I_TEMAC/idelayctrl_reset_0_r_
   7" has the property IOB=FORCE, but it did not join an IO component because it
   is not connected to any IO element

Implementation options are the same (ISE defaults strategy) in XPS and planAhead. Is someone know why I can not implement the same design with the same option?

Thanks for helping

Cédric
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2 Replies
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Visitor
Visitor
10,445 Views
Registered: ‎04-27-2010

Hi,

 

Do you need more informations to understand my pb? Does anyone know what happened?

 

Actually, I isolate the pb. Only the DDR2 can't be implemented with planAhead 11.5. I changed it for an SRAM and everything works but I still want to know why! Is it possible that the IP evolve in XPS and not in planAhead?

 

Thanks,

 

Cedric

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Xilinx Employee
Xilinx Employee
10,386 Views
Registered: ‎05-14-2008

I suspect there are some UCFs of the IP cores in your design in the XPS project. But you only add the top level UCF to the PlanAhead project. Try to find the IP UCFs and copy the contents to the top level UCF.

 

Thanks,

Vivian

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