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rikusleroux
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Explorer
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Registered: ‎05-21-2009

Implementing a PowerPC in PlanAhead

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Good day,

 

Can someone please help me with an issue I'm having?

 

I'm trying to implement a reconfigurable application in PlanAhead. I've worked through the tutorial and was able to implement my own application with a module blinking an LED. However, I'm now struggling to add a PowerPC to the design (it is implemented on a Virtex-5). I just added the PowerPC system to my top level design in ISE. Implementing a static application, everything works fine with the PowerPC included.

 

However, when I design the reconfigurable application in a similar way indicated by UG743. It seems like the PowerPC is not functioning. Initially, I figured it was the way I added the ELF file into the bitstream using data2mem, but I'm gradually starting to suspect my implementation of the PowerPC in PlanAhead. What is the best way to do it? The way it is currently implemented results in pr_verification failing due to static logic being "inconsistent between configurations". In my first design run my static logic, PowerPC and reconfigurable logic is "Implemented". In my second design run, PowerPC and static logic is "Imported" but reconfiguration is "Implemented".

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cgauer
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Registered: ‎09-21-2010

I've never done anything with Power PCs, but I'll see if I can be helpful.

 

1.  When you create your PlanAhead project and select the top-level netlist file, PlanAhead is likely to automatically import any lower-level netlist files you need, if they share a directory with your top netlist file.  However, if it does not import them automatically, you may need to add them to the project.  If any netlist files are missing, when you open the netlist design, PlanAhead should warn you that some instances have been converted to black boxes.

 

2 and 3.  I don't think that is necessary.  While I have never used  Power PC, I have created systems that had other resources which were only located in one part of the FPGA.  As long as your Power PC is in the static region of your design, PlanAhead should automatically place it where it needs to be.

 

4. You should definitely make a new strategy and point it to your BMM file.  If you haven't been doing this, I suspect this is your problem.  Basically, what this will do is give the mapping tools and Bitgen information about the block RAMs your processor needs.  Bitgen will then spit out a back-annotated BMM file, which will be named <your_bmm_name>_bd.bmm, which describes where the tools put those block RAMs.  You will need this later when you use Data2Mem to merge your program data into the bitstream.  Using the _bd.bmm file that was generated for your static design will probably not work -- you need the fresh one that is made by PlanAhead, and to get that file made, you need to include the -bm option in your strategy.

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rikusleroux
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Registered: ‎05-21-2009

I see I'm not getting any response, so allow my to elaborate. Maybe I was a bit unclear.

 

My problem is basically that using PlanAhead to implement a partial reconfigurable application, it seems like my PowerPC is not instantiated/placed on the Virtex-5. The reason I'm saying it is PlanAhead, is because I implemented exactly the same application statically (I thus removed all reconfigurable modules and implemented one as a static) using the ISE, and the application works fine. However, generating the bitstream (only one to test the application as a comparison to the static case), I'm not getting any response from the PowerPC. This led me to believe that I'm doing something wrong in implementing the PowerPC in PlanAhead.

 

My hierarchy in the application is as follows:

 

Top level (developed in ISE) -> PowerPC (system designed in EDK and implemented in Top) -> ELF file (generated using SDK).

 

Now, here are my questions:

 

1. Using UG744 as reference, I see that the Microblaze is the top level and that all the components of the system are available as the netlist. However, in my case I have a VHDL project as a top level. Is it thus sufficient to only select my top netlist in PlanAhead or should I add the PowerPC system components to the sources as NGC-files?

 

2. Since the PowerPC is a hard-core processor, it has only one location on the FPGA. Should I draw a new Pblock for the PowerPC on that location and assign it to that Pblock?

 

3. Should I set the PowerPC as a partition? I see UG744 has an option of adding the module as a black box. In ISE 13.1 I only have the option to set it as a reconfigurable partition, or a partition.

 

4. Lastly, referring back to UG744, I see that they create a new strategy by adding a -bm switch and selecting the .bmm-file (step 8-1-9 in UG744). Why is this necessary? Should I do this as well for my application?

 

Sorry for the lots of questions. It just feels like the is so many combinations to try in PlanAhead, and I'm not sure which one.

 

Thanks again.

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cgauer
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19,116 Views
Registered: ‎09-21-2010

I've never done anything with Power PCs, but I'll see if I can be helpful.

 

1.  When you create your PlanAhead project and select the top-level netlist file, PlanAhead is likely to automatically import any lower-level netlist files you need, if they share a directory with your top netlist file.  However, if it does not import them automatically, you may need to add them to the project.  If any netlist files are missing, when you open the netlist design, PlanAhead should warn you that some instances have been converted to black boxes.

 

2 and 3.  I don't think that is necessary.  While I have never used  Power PC, I have created systems that had other resources which were only located in one part of the FPGA.  As long as your Power PC is in the static region of your design, PlanAhead should automatically place it where it needs to be.

 

4. You should definitely make a new strategy and point it to your BMM file.  If you haven't been doing this, I suspect this is your problem.  Basically, what this will do is give the mapping tools and Bitgen information about the block RAMs your processor needs.  Bitgen will then spit out a back-annotated BMM file, which will be named <your_bmm_name>_bd.bmm, which describes where the tools put those block RAMs.  You will need this later when you use Data2Mem to merge your program data into the bitstream.  Using the _bd.bmm file that was generated for your static design will probably not work -- you need the fresh one that is made by PlanAhead, and to get that file made, you need to include the -bm option in your strategy.

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rikusleroux
Explorer
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11,742 Views
Registered: ‎05-21-2009

Hi cgauer

 

Thanks you very much! You were a tremendous help! I don't really know if it would make a difference to specify the location of the PowerPC or if it is necessary to define it as a partition, but I modified my application so that only the location of the reconfigurable module is specified (as you stated in 2 and 3 in your post). However, it was nr. 4 that sealed the deal. Even though I created a new strategy and synthesized all my runs using my custom strategy, I was unaware that a new .bmm file was created and newer used it with Data2mem. The moment I used the newly generated bmm-file to create my bitstream, it worked like a charm.

 

Thanks again for your help! Much appreciated!

 

Edited: I think I should probably add that in my case it was required to add the netlist files of the PowerPC into the design. Without loading it, the PowerPC is added as a black box.

 

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