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Observer byusean
Observer
4,149 Views
Registered: ‎01-25-2017

Implementing an OOC module gives error of unbuffered src and loads

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I'm trying to accomplish a simple Out-Of-Context implementation of a counter, mostly as a way to get myself up-to-speed on OOC design flows. I went through the Vivado Design Suite Tutorial: Hierarchical Design located here (which is the latest tutorial I could find on the subject) and decided I would try and create my own design instead of relying on the copious amounts of Verilog and XDC and TCL that comes pre-packaged for you. So, here's my simple counter:

 

module counter(clk, rst, en, blink);
    parameter width = 26;
    
    output  blink;
    input   clk, en, rst;
    reg     [width-1:0] count = 0;
    reg     blink = 0;
    
    always @(posedge clk) 
    begin
        if (rst == 1'b1) 
            count = 0;
        else if (en == 1'b1)
            count = count + 1;

        if (count[width-1] == 1'b1)
            blink = 1'b1;
        else
            blink = 1'b0;
    end
endmodule

I modified the design.tcl file that is provided in the tutorial mentioned above and (hopefully) created the module_phys.xdc, module_ooc_timing.xdc, module_ooc_budget.xdc, and module_ooc_optimize.xdc files correctly. Below I'll show my design.tcl file. It is essentially the same design.tcl file provided in the tutorial, but everything except for the OOC Synthesis and Implementations are stripped out.

###############################################################
###   Tcl Variables
###############################################################
#set tclParams [list <param1> <value> <param2> <value> ... <paramN> <value>]
set tclParams [list hd.visual 1 \
              ]

#Define location for "Tcl" directory. Defaults to "./Tcl"
set tclHome "./Tcl"
if {[file exists $tclHome]} {
   set tclDir $tclHome
} elseif {[file exists "./Tcl"]} {
   set tclDir  "./Tcl"
} else {
   error "ERROR: No valid location found for required Tcl scripts. Set \$tclDir in design.tcl to a valid location."
}

###############################################################
### Part Variables - Define Device, Package, Speedgrade 
###############################################################
set device       "xc7a100t"
set package      "csg324"
set speed        "-1"
set part         $device$package$speed

###############################################################
###  Setup Variables
###############################################################
####flow control
set run.oocSynth   1
set run.oocImpl    1

####Report and DCP controls - values: 0-required min; 1-few extra; 2-all
set verbose      1
set dcpLevel     1

####Output Directories
set synthDir  "./Synth"
set implDir   "./Implement"
set dcpDir    "./Checkpoint"

####Input Directories
set srcDir     "./Sources"
set rtlDir     "$srcDir/hdl"
set prjDir     "$srcDir/prj"
set xdcDir     "$srcDir/xdc"
set coreDir    "$srcDir/cores"
set netlistDir "$srcDir/netlist"

####Source required Tcl Procs
source $tclDir/design_utils.tcl
source $tclDir/synth_utils.tcl
source $tclDir/impl_utils.tcl
source $tclDir/hd_floorplan_utils.tcl

####################################################################
### OOC Module Definition and OOC Implementation for each instance
####################################################################
set module1 "counter"
add_module $module1
set_attribute module $module1 prj          $prjDir/$module1.prj
set_attribute module $module1 synth        ${run.oocSynth}

set instance "counter0"
add_ooc_implementation $instance
set_attribute ooc $instance   module       $module1
set_attribute ooc $instance   inst         $instance
set_attribute ooc $instance   hierInst     $instance
set_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc         \
                                                 $xdcDir/${instance}_ooc_timing.xdc   \
                                                 $xdcDir/${instance}_ooc_budget.xdc   \
                                                 $xdcDir/${instance}_ooc_optimize.xdc \
                                           ] 
set_attribute ooc $instance   impl         ${run.oocImpl}
set_attribute ooc $instance   preservation routing

########################################################################
### Task / flow portion
########################################################################

# Build the designs
source $tclDir/run.tcl

exit

When I run the design.tcl file from the Vivado shell with the following command

vivado -mode batch -source design.tcl -notrace

I get the following errors during the implementation phase of the Vivado batch run:

ERROR: [Place 30-188] UnBuffered IOs: blink has following unbuffered src :  blink_reg(FDRE)
ERROR: [Place 30-188] UnBuffered IOs: clk has following unbuffered loads :  blink_reg(FDRE)  count_reg[0](FDRE)  count_reg[10](FDRE)  count_reg[11](FDRE)  count_reg[12](FDRE)  count_reg[13](FDRE)  count_reg[14](FDRE)  count_reg[15](FDRE)  count_reg[16](FDRE)  count_reg[17](FDRE)  count_reg[18](FDRE)  count_reg[19](FDRE)  count_reg[1](FDRE)  count_reg[20](FDRE)  count_reg[21](FDRE)  count_reg[22](FDRE)  count_reg[23](FDRE)  count_reg[24](FDRE)  count_reg[2](FDRE)  count_reg[3](FDRE)  count_reg[4](FDRE)  count_reg[5](FDRE)  count_reg[6](FDRE)  count_reg[7](FDRE)  count_reg[8](FDRE)  count_reg[9](FDRE)
ERROR: [Place 30-188] UnBuffered IOs: en has following unbuffered loads :  count[3]_i_5(LUT2)
ERROR: [Place 30-188] UnBuffered IOs: rst has following unbuffered loads :  blink_reg(FDRE)  count_reg[0](FDRE)  count_reg[10](FDRE)  count_reg[11](FDRE)  count_reg[12](FDRE)  count_reg[13](FDRE)  count_reg[14](FDRE)  count_reg[15](FDRE)  count_reg[16](FDRE)  count_reg[17](FDRE)  count_reg[18](FDRE)  count_reg[19](FDRE)  count_reg[1](FDRE)  count_reg[20](FDRE)  count_reg[21](FDRE)  count_reg[22](FDRE)  count_reg[23](FDRE)  count_reg[24](FDRE)  count_reg[2](FDRE)  count_reg[3](FDRE)  count_reg[4](FDRE)  count_reg[5](FDRE)  count_reg[6](FDRE)  count_reg[7](FDRE)  count_reg[8](FDRE)  count_reg[9](FDRE)
ERROR: [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
INFO: [Vivado 12-618] Current instance is the top level of design 'design_1'.
#HD: Writing checkpoint ./Implement/counter0/counter0_place_design_error.dcp for debug.
ERROR: [Common 17-69] Command failed: Placer could not place all instances

ERROR: place_design command "place_design" failed.
See log file ./Implement/counter0/counter0_place_design.log for more details.
    while executing
"error $errMsg"
    (procedure "command" line 66)
    invoked from within
"command "$impl_step" "$log""
    (procedure "impl_step" line 90)
    invoked from within
"impl_step place_design $ooc_inst $place_options $place_directive ${place.pre}"
    (procedure "ooc_impl" line 156)
    invoked from within
"ooc_impl $ooc_impl"
    ("foreach" body line 8)
    invoked from within
"foreach ooc_impl $ooc_implementations {
      if {[get_attribute ooc $ooc_impl impl]} {
         #Override directives if directive file is specified
 ..."
    invoked from within
"if {[llength $ooc_implementations] > 0} {
   foreach ooc_impl $ooc_implementations {
      if {[get_attribute ooc $ooc_impl impl]} {
         #Overrid..."
    (file "./Tcl/run.tcl" line 41)

    while executing
"source $tclDir/run.tcl"
    (file "design.tcl" line 83)
INFO: [Common 17-206] Exiting Vivado at Wed Jan 25 15:45:46 2017...

It would seem as though the tools would buffer the IO's themselves, but is there something that I need to do in order to encourage the tools to do that for me?

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
6,815 Views
Registered: ‎04-16-2008

Re: Implementing an OOC module gives error of unbuffered src and loads

Jump to solution

Thanks for providing all the files necessary to reproduce this. The error message is not as good as it could be in this case, and so it is not immediate obvious what is happening.

 

However, as I started setting up my own area with the files you provided, I took a look at the XDC files and noticed a couple things.

1. There are IO properties (IOSTANDARD/PACKAGE_PIN) inside of both "phys.xdc" and "budget.xdc", but you don't instantiate any IO Buffers inside of your module.  In the OOC implementation, you should only have IO information on ports that have IO buffers instantiated on them. No IO buffers are ever inferred by the tools in OOC mode. You need to either manually instantiate them, or add the IO_BUFFER_TYPE==IBUF (or OBUF), and then add appropriate IO_BUFFER_TYPE==NONE to your corresponding top-level ports so you don't end up with series/redundant IO buffers.  I think this was the root cause of the error you were seeing. I commented all of these out.

 

2. I noticed your Pblock wasn't getting read in correctly. Check the critical.log file to note the following warning during link_design.

	CRITICAL WARNING: [Vivado 12-2126] Cannot specify '-cells' with '-top'. [./counter/Sources/xdc/counter0_phys.xdc:7]
	CRITICAL WARNING: [Vivado 12-1040] No pblock name found. [./counter/Sources/xdc/counter0_phys.xdc:8]

For the first Critical Warnings... in Tcl, you can't add a comment (#) to the end of a line without a semi-colon (;) to separate them (stating the end of one command the start of another). In the following command from your XDC, either delete the comment (#[get_cells -quiet [list myCounter]]) after -top, or add a semi-colon after -top;.

add_cells_to_pblock [get_pblocks pblock_counter] -top  #[get_cells -quiet [list myCounter]]

If you don't do this, you won't get any error, but you won't have a Pblock on your module either, which was not your intent.

 

 

For the second Critical Warning above, the issue is your command to resize the Pblock references "pblock_1", which does not exist (your pblock is called "pblock_counter". If you don't fix this, you'll get other errors at the final DRC check:

 HDOOC-4#1: 34 Cells are found with no placement constraints. Failure to control placement of logic with either a Pblock or a LOC constraint may result in placement conflicts if the out-of-context implementation results are reused in a top-level design. The following is a list of cells (up to the first 15) with no placement constraints:
        blink_reg (FDRE)
        blink_reg_i_1 (CARRY4)
        count[3]_i_5 (LUT2)
        count_reg[0] (FDRE)
        count_reg[10] (FDRE)
        count_reg[11] (FDRE)

This occurs because the Pblock never got a valid range assigned to it. 

 

If you fix these couple items, your design will then complete as intended.

 Counter OOC implementation

 

 

If you are using the OOC implementation for analysis purposes (ie. you don't intend to reuse the OOC place/route results), then you're pretty good here.  If you do plan to do the Module Reuse flow, you need to make sure you setup all of the necessary constraints (PartPins, HD.CLK_SRC, clock uncertainty, etc) as the tutorial shows.

 

Hope this helps!

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3 Replies
Observer byusean
Observer
4,146 Views
Registered: ‎01-25-2017

Re: Implementing an OOC module gives error of unbuffered src and loads

Jump to solution
The counter0_ooc_timing.xdc and counter0_ooc_optimize.xdc files are not included because they are empty.
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Xilinx Employee
Xilinx Employee
6,816 Views
Registered: ‎04-16-2008

Re: Implementing an OOC module gives error of unbuffered src and loads

Jump to solution

Thanks for providing all the files necessary to reproduce this. The error message is not as good as it could be in this case, and so it is not immediate obvious what is happening.

 

However, as I started setting up my own area with the files you provided, I took a look at the XDC files and noticed a couple things.

1. There are IO properties (IOSTANDARD/PACKAGE_PIN) inside of both "phys.xdc" and "budget.xdc", but you don't instantiate any IO Buffers inside of your module.  In the OOC implementation, you should only have IO information on ports that have IO buffers instantiated on them. No IO buffers are ever inferred by the tools in OOC mode. You need to either manually instantiate them, or add the IO_BUFFER_TYPE==IBUF (or OBUF), and then add appropriate IO_BUFFER_TYPE==NONE to your corresponding top-level ports so you don't end up with series/redundant IO buffers.  I think this was the root cause of the error you were seeing. I commented all of these out.

 

2. I noticed your Pblock wasn't getting read in correctly. Check the critical.log file to note the following warning during link_design.

	CRITICAL WARNING: [Vivado 12-2126] Cannot specify '-cells' with '-top'. [./counter/Sources/xdc/counter0_phys.xdc:7]
	CRITICAL WARNING: [Vivado 12-1040] No pblock name found. [./counter/Sources/xdc/counter0_phys.xdc:8]

For the first Critical Warnings... in Tcl, you can't add a comment (#) to the end of a line without a semi-colon (;) to separate them (stating the end of one command the start of another). In the following command from your XDC, either delete the comment (#[get_cells -quiet [list myCounter]]) after -top, or add a semi-colon after -top;.

add_cells_to_pblock [get_pblocks pblock_counter] -top  #[get_cells -quiet [list myCounter]]

If you don't do this, you won't get any error, but you won't have a Pblock on your module either, which was not your intent.

 

 

For the second Critical Warning above, the issue is your command to resize the Pblock references "pblock_1", which does not exist (your pblock is called "pblock_counter". If you don't fix this, you'll get other errors at the final DRC check:

 HDOOC-4#1: 34 Cells are found with no placement constraints. Failure to control placement of logic with either a Pblock or a LOC constraint may result in placement conflicts if the out-of-context implementation results are reused in a top-level design. The following is a list of cells (up to the first 15) with no placement constraints:
        blink_reg (FDRE)
        blink_reg_i_1 (CARRY4)
        count[3]_i_5 (LUT2)
        count_reg[0] (FDRE)
        count_reg[10] (FDRE)
        count_reg[11] (FDRE)

This occurs because the Pblock never got a valid range assigned to it. 

 

If you fix these couple items, your design will then complete as intended.

 Counter OOC implementation

 

 

If you are using the OOC implementation for analysis purposes (ie. you don't intend to reuse the OOC place/route results), then you're pretty good here.  If you do plan to do the Module Reuse flow, you need to make sure you setup all of the necessary constraints (PartPins, HD.CLK_SRC, clock uncertainty, etc) as the tutorial shows.

 

Hope this helps!

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Observer byusean
Observer
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Registered: ‎01-25-2017

Re: Implementing an OOC module gives error of unbuffered src and loads

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woodsd,

 

Thank you so much for your response. I am ashamed to not have realized the critical warnings in the critical.log file, so thank you for drawing my attention to it. In implementing the suggestions you posted I was able to get the design to synthesize and implement without any errors! However, I only was able to get it to do so when I had the following lines in my counter.v file:

 

(* io_buffer_type="OBUF" *)
    output  blink;
(* io_buffer_type="IBUF" *)
    input   clk;
(* io_buffer_type="IBUF" *)
    input   en;
(* io_buffer_type="IBUF" *)
    input   rst;
    reg     [width-1:0] count = 0;
    reg     blink = 0;

and the following code in my *.xdc files:

 

 

set_property IO_BUFFER_TYPE none [get_ports blink];      #from counter0_phys.xdc
set_property IO_BUFFER_TYPE none [get_ports en]          #from counter0_phys.xdc
set_property IO_BUFFER_TYPE none [get_ports rst]         #from counter0_phys.xdc
set_property IO_BUFFER_TYPE none [get_ports clk] #from counter0_ooc_budget.xdc

I also tried to instead run the flow with the clk property set to any of the CLOCK_BUFFER_TYPE's listed here, namely BUFG, BUFH, BUFIO, BUFMR, and BUFR.

...
    output  blink;
(* clock_buffer_type="BUFG" *)
    input   clk;
(* io_buffer_type="IBUF" *)
...

Could you explain to me a little bit about why those return almost the exact same error as I was getting before (meaning that it didn't infer a buffer)?

 

--Sean

 

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