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janet
Observer
Observer
1,078 Views
Registered: ‎07-12-2018

Is there a way that I can generated different bit files by using different area constaints?

Hi All,

 

I am encounterring a route congestion problem.

I want to explore with different area constraints.

Is there a way that I can have different area constraints for different buildings at the same time.

So after the bit gen, I can have different bit files for each building all in once.

 

Thanks~! 

0 Kudos
2 Replies
tedbooth
Scholar
Scholar
1,069 Views
Registered: ‎03-28-2016

Check out UG892, Chapter 3, "Configuring Synthesis and Implementation Runs":

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug892-vivado-design-flows-overview.pdf

 

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
tanders
Xilinx Employee
Xilinx Employee
1,054 Views
Registered: ‎03-31-2011

You can create different constraint files for the different constraints, create separate runs that use them, and the review those runs independently.

e.g.
Constraint_file_1 -> Impl_1
Constraint_file_2 -> Impl_2
etc...