UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer janet
Observer
697 Views
Registered: ‎07-12-2018

Is there a way that I can generated different bit files by using different area constaints?

Hi All,

 

I am encounterring a route congestion problem.

I want to explore with different area constraints.

Is there a way that I can have different area constraints for different buildings at the same time.

So after the bit gen, I can have different bit files for each building all in once.

 

Thanks~! 

0 Kudos
2 Replies
Voyager
Voyager
688 Views
Registered: ‎03-28-2016

Re: Is there a way that I can generated different bit files by using different area constaints?

Check out UG892, Chapter 3, "Configuring Synthesis and Implementation Runs":

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug892-vivado-design-flows-overview.pdf

 

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Xilinx Employee
Xilinx Employee
673 Views
Registered: ‎03-31-2011

Re: Is there a way that I can generated different bit files by using different area constaints?

You can create different constraint files for the different constraints, create separate runs that use them, and the review those runs independently.

e.g.
Constraint_file_1 -> Impl_1
Constraint_file_2 -> Impl_2
etc...