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marquesni
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Registered: ‎12-02-2009

LUT placement

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Hello,

I carry out a project with a reconfigurable architecture. I use PlanAhead (v 13.2) for the placement of my PR and the importation of my RM. In my PlanAhead project I added a file of constraint (*.ucf type).


I would like to force the placement of my Pin Partition. 


Example of constraint in the file *.ucf:
PIN "top_1_zone_0/top_1_zone_0/Inst_RM_10.rst_rm_2_i" LOC = SLICE_X38Y40;
PIN "top_1_zone_0/top_1_zone_0/Inst_RM_10.rst_rm_2_i" BEL = D6LUT;

 

I would add a third constraint to select which input of the LUT I want to connect (eg A6). 
Is there an option(ucf constraint or other)  to force the input of a logic element of a LUT.
 
 

Best Regards

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woodsd
Xilinx Employee
Xilinx Employee
18,576 Views
Registered: ‎04-16-2008

Try opening your place and routed design.  Then Tools>Directed Routing Constraints.  You can select the nets that you want to write out contraints for, and click Ok. When you save the design you will get a UCF (in the directory where your NCD was) with constraints like:

 

NET "static_IIC_INIT/bit_count[25]"
ROUTE="{3;1;6vlx240tff1156;d705ae6!-1;46408;-73568;S!0;-683;-80!1;0;384!"
"1;0;320!2;683;-336;L!3;843;176;L!}";

 

This method uses the initial placement/routing of the tools, and presevers it for future iterations.  It is also possible to hand route/modify the routing in FPGA Editor and then write the constraints out.  

View solution in original post

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marquesni
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Registered: ‎12-02-2009

Hello,


Is it not possible to fix the connection of a LUT with the addition of constraint in a *. XDL file?

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woodsd
Xilinx Employee
Xilinx Employee
12,253 Views
Registered: ‎04-16-2008

The two constraints you show are placement constraints (site/bel locations).  To fix the routing to a specific pin, you could try a Directed Routing constraint.  You can create these in FPGA Editor (Tools > Directed Routing Constraints).  For more information search the XIlinx Website for Directed Routing Constraint.

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marquesni
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Registered: ‎12-02-2009

Hello,

I looked in FPGA Editor (Tools> Directed Routing contraintes) but I do not find anything to fix therouting to a specific pin.

I also looked at the Xilinx website for Directed Routing contraintes, but I do not find anything.

Can you give me more detail?

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woodsd
Xilinx Employee
Xilinx Employee
18,577 Views
Registered: ‎04-16-2008

Try opening your place and routed design.  Then Tools>Directed Routing Constraints.  You can select the nets that you want to write out contraints for, and click Ok. When you save the design you will get a UCF (in the directory where your NCD was) with constraints like:

 

NET "static_IIC_INIT/bit_count[25]"
ROUTE="{3;1;6vlx240tff1156;d705ae6!-1;46408;-73568;S!0;-683;-80!1;0;384!"
"1;0;320!2;683;-336;L!3;843;176;L!}";

 

This method uses the initial placement/routing of the tools, and presevers it for future iterations.  It is also possible to hand route/modify the routing in FPGA Editor and then write the constraints out.  

View solution in original post

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gndrix
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Registered: ‎04-25-2011

Hello, I'm trying to do the same that marquesini, fix  the position of a pin in a proxy LUT for partial reconfiguration. Could it be possible to do it modifying the XDL file generated with xdl -ncd2xdl and go back again to ncd?. I think it's possible, however, would I need  to modify nets or just the SLICE instance?

 

Thanks in advance.

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woodsd
Xilinx Employee
Xilinx Employee
12,129 Views
Registered: ‎04-16-2008

This question is spread out through a couple forum posts, but I think this one has the answer you want:

 

http://forums.xilinx.com/t5/Hierarchical-Design/LUT-input-of-the-PROXY-LOGIC/m-p/221455#M569

 

Look at the LOCK_PINS constraint.

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