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2,567 Views
Registered: ‎11-10-2017

Library declaration in verilog

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We can use following very simple declaration in VHDL. But how to declare it in verilog in a simple way?

 

LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;

 

 

Thanks.

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Scholar markcurry
Scholar
3,571 Views
Registered: ‎09-16-2009

Re: Library declaration in verilog

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This is going to tread awfully close to starting a language war, and that's not my intention...

 

The library features in SystemVerilog were added, IMHO, rather late, and intended to target VHDL users coming over to Verilog.  In my experiences, I've not yet seen any usage of these features in the wild.  Of course most of my colleagues are longtime Verilog users.

 

Verilog did NOT have these language features for a long time. Verilog users have different methods of solving whatever problems those features were intended to address.  In short, most Verilog users don't need / use "libraries" (as defined in the language).

 

Regards,

 

Mark

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Moderator
Moderator
2,539 Views
Registered: ‎09-15-2016

Re: Library declaration in verilog

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Hi @xingwang_chen

 

There is no concept of library in verilog. Verilog header files allow you to store commonly used modules and components that you can use in your Verilog files.

https://www.xilinx.com/itp/xilinx10/isehelp/ise_c_working_with_verilog_header_files.htm

 

Regards

Rohit

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Regards
Rohit
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2,414 Views
Registered: ‎01-08-2012

Re: Library declaration in verilog

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thakurr wrote:

There is no concept of library in verilog.


The language reference manual suggests otherwise.  Try reading chapter 33 of IEEE Std 1800-2012 (etc.).

 

Did you mean to say "There is no concept of a library for Verilog in Vivado" instead?

 

Allan

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Scholar markcurry
Scholar
3,572 Views
Registered: ‎09-16-2009

Re: Library declaration in verilog

Jump to solution

 

This is going to tread awfully close to starting a language war, and that's not my intention...

 

The library features in SystemVerilog were added, IMHO, rather late, and intended to target VHDL users coming over to Verilog.  In my experiences, I've not yet seen any usage of these features in the wild.  Of course most of my colleagues are longtime Verilog users.

 

Verilog did NOT have these language features for a long time. Verilog users have different methods of solving whatever problems those features were intended to address.  In short, most Verilog users don't need / use "libraries" (as defined in the language).

 

Regards,

 

Mark

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2,362 Views
Registered: ‎11-10-2017

Re: Library declaration in verilog

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Thank you a lot Mark and all. My intention was just to check if I'm the only one don't know the story behind. If this is the feature difference between VHDL and Verilog, that's fine for me.

 

Best regards.

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