MMCM Dynamic Reconfiguration parameter options

[ivars211]

Hi, a general question about AR# 71112 - I have calculated and implemented MMCM with DRP. 

Is there any difference between the values you choose for multiplier and divider? 

For example, with input clock of 100mhz I can get 200Mhz in two ways (Ultrascale+)

CLKFBOUT_MULT = 16; DIVCLK_DIVIDE = 1; DIVIDE @ CLKOUT0 = 8; Thus 100*16/(1*8) = 200Mhz

However, I can also do it as follows:

CLKFBOUT_MULT = 8; DIVCLK_DIVIDE = 1; DIVIDE @ CLKOUT0 = 4; Thus 100*8/(1*4) = 200Mhz

Is one better than the other or it doesn't matter? I read something about jitter being better when the multipliers are closer to the upper 1600mhz limit.

Appreciate any comment.

[miker]

@ivars211 

You can use the Clocking Wizard to assist you in making the best decision.  You can enter the incoming clock frequency and desired output clock frequency and see what they recommend.  You can then select the "MMCM Settings" tab and select "Allow Override Mode".  This allows you to dial in your settings and verify on the "Summary" tab the jitter produced by each configuration.

For example, a 100MHz input clock generating a 200MHz output clock using either a CLKFB_MULT_F (UltraScale) of 12 (recommended), 16, or 8 and a CLKOUT0_DIVIDE of 6,  or 3, 8, or 4 respectively.

Recommended:  M=12 / D=6

Option 1:  M=16 / D=8

Option 2:  M=8 / D=4

[ivars211]

Appreciate your response and I know that I can check it there.

From these three examples, the M=16/D=8 produces the least jitter and least phase error, so am I understanding this correctly - it is the most desirable out of the three? Even though the recommended is M=12/D=6? 

[miker · Accepted solution]

@ivars211 

You can reference the Clocking Wizard LogiCORE IP Product Guide (PG065; v6.0).  It discusses the Jitter Optimization options (Balanced, Minimize Output Jitter, Maximize Input Jitter Filtering) so the Clocking Wizard will recommend the M/D values based on your Jitter Optimization choice.  Be sure to determine what your ultimate goal would be in terms of power, jitter, and clock phase error.