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Observer
Observer
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Registered: ‎11-14-2017

My vivado2018.1 crashed when i did the partial reconfiguration with ug947

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Hi,everyone,

   I bought the VCU108 board to learn the partial reconfiguration recently.

   Bur I have a problem when i did the partial reconfiguration with the Lab 6 in ug947.

   I configured the partial reconfiguration IP core as the Lab 6 in ug947. Then i used the cd command to find the design.tcl and choosed the Run Tcl Script in the Tools menu. Because the command"vivado -mode tcl -source design.tcl" in Lab6 doesn't work.

   After i clicked design.tcl in sub-menu, the vivado began to run with a lot of warnnings and a few of errors. After about 1 hour the vivado 2018.1 crashed.

   Is there any error operation i did?

   OR is there any method can figure it out?

 

thanks,

crazywolf.

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Xilinx Employee
Xilinx Employee
3,239 Views
Registered: ‎11-17-2008

@crazywolf,

 

Please make sure you are following the tutorial instructions in UG947.  On page 130, step 1 compiles the design to where you are now, but then step 2 takes those bitstreams and packs them in a PROM image.  These two steps are each unique calls to Vivado (vivado -mode tcl -source design.tcl), so you don't need to have Vivado open to start, but you could open a Vivado session and source the script directly from within (from the Tcl Console: source design.tcl).

 

Yes, you can open the Vivado Hardware Manager and download bitstreams directly via JTAG.  I don't have the exact bitstream file names handy, but the naming (and bitstream sizes) are pretty obvious.  Since you are using UltraScale, be sure to apply the clearing bitstream before the next partial, as described at the end of lab 2.

 

Should you ignore the errors?  I am going to say no, do not ignore the errors.  How are you getting the .Xil directory in your script path?  Can you look into the synthesis log to see if there are more details?  If synthesis isn't picking up constraints correctly, it might have an impact on the end result.

 

What do you mean "see the whole project"?  This example is run in the scripted non-project mode, so to "see" the project is to look at the sources and logs and resulting checkpoints, all the files along the way.  It sounds like you want to work within the graphical user environment, where the source hierarchy and floorplan and other pieces are laid out visually.  In that case, take a look at labs 3 and 4 in this same document -- they run through the GUI-centric project environment.  You can use the same sources to rebuild lab 6, using the process described in labs 3 and 4.

 

thanks,

david.

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Moderator
Moderator
2,560 Views
Registered: ‎01-16-2013

@crazywolf,

 

Can you share the vivado.log file when using Lab6? What is the OS are you using?

Make sure there are no spaces or special characters in the project directory path. 

 

--Syed

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Observer
Observer
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Registered: ‎11-14-2017

@syedz,

   Please tell me where can i find the vivado.log file?

   I use the windows 7 OS

   I think there are no spaces or special characters. I put the prc_us floder in the E root directory.

 

thanks,

crazywolf.

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Moderator
Moderator
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Registered: ‎01-16-2013

@crazywolf,

 

From vivado TCL console, just type "pwd" to get the directory which will have vivado.log file. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Observer
Observer
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Registered: ‎11-14-2017

@syedz,

  Because the crash of my vivado, i have to open a new vivado.

  I go to the project before vivado crashed and type"pwd" in TCL

  But i can only find command.log  critical.log  pr_verify_results.log  run.log these 5 .log files without vivado,log.

  Should i share these files ?

 

thanks,

crazywolf.

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Moderator
Moderator
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Registered: ‎01-16-2013

@crazywolf,

 

Yes share these files. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Observer
Observer
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Registered: ‎11-14-2017

@syedz

     These are all .log files in the folder.

 

thanks,

crazywolf.

 

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Xilinx Employee
Xilinx Employee
2,445 Views
Registered: ‎11-17-2008

@crazywolf,

 

Are you sure it crashed?  Looking at those log files, I see that PR Verify has completed successfully and write_bitstream was run, and I don't see a crash.  (I do see that some constraint files are in a path containing .Xil, so check how you're launching Vivado and the scripts.)  Please note that design.tcl concludes with an "exit" command, so out of the box, it is expected to close the Vivado session upon completion.  From the logs and your description (an hour runtime is expected), everything sounds fine to me.  Do you see bitstreams?

 

thanks,

david.

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Observer
Observer
2,402 Views
Registered: ‎11-14-2017

@davidd,

    Thanks a lot for your answers.

    I can find a lot of bit files in the Bit streams folder. However,they are seem all the part of the project, I cannot find the "top" bit files, so which one should i download in the boards?

    And if the design.tcl include an "exit" command, should i open a new vivado project with VCU108 board and just open the hardware manger to download the bit streams without any other operation?

    And there are actually have some errors when running the design.tcl. Should i ignore them?

    I run the design.tcl by clicking the Run tcl scripts in the Tools menu. Because the command in ug947 doesn't at all. Am i run in a right way?

    Last,if i want to see the whole project,what should i do? Because i want to build my own partial reconfiguration project,so i have to learn see the whole project and imitate it.

 

thanks,

crazywolf.

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Highlighted
Xilinx Employee
Xilinx Employee
3,240 Views
Registered: ‎11-17-2008

@crazywolf,

 

Please make sure you are following the tutorial instructions in UG947.  On page 130, step 1 compiles the design to where you are now, but then step 2 takes those bitstreams and packs them in a PROM image.  These two steps are each unique calls to Vivado (vivado -mode tcl -source design.tcl), so you don't need to have Vivado open to start, but you could open a Vivado session and source the script directly from within (from the Tcl Console: source design.tcl).

 

Yes, you can open the Vivado Hardware Manager and download bitstreams directly via JTAG.  I don't have the exact bitstream file names handy, but the naming (and bitstream sizes) are pretty obvious.  Since you are using UltraScale, be sure to apply the clearing bitstream before the next partial, as described at the end of lab 2.

 

Should you ignore the errors?  I am going to say no, do not ignore the errors.  How are you getting the .Xil directory in your script path?  Can you look into the synthesis log to see if there are more details?  If synthesis isn't picking up constraints correctly, it might have an impact on the end result.

 

What do you mean "see the whole project"?  This example is run in the scripted non-project mode, so to "see" the project is to look at the sources and logs and resulting checkpoints, all the files along the way.  It sounds like you want to work within the graphical user environment, where the source hierarchy and floorplan and other pieces are laid out visually.  In that case, take a look at labs 3 and 4 in this same document -- they run through the GUI-centric project environment.  You can use the same sources to rebuild lab 6, using the process described in labs 3 and 4.

 

thanks,

david.

View solution in original post

Highlighted
Observer
Observer
1,433 Views
Registered: ‎11-14-2017

@davidd,

     Thanks a lot for your answers.

       Now i can run the example successfully.

 

 

thanks,

crazywolf.

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