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byusean
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Registered: ‎01-25-2017

OOC module should not be changed by top design

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I am trying to implement a design with one out of context module, an AES 128 block. Functionality and efficiency are not as important as physical layout to me right now.

 

Using the design flow provided in UG946, the Hierarchical Design Flow Tutorial, I can run oocSynth and oocImpl perfectly and the result is shown below:

 

aes_128_0_synth_impl.png

 

Then, when I run the topSynth, tdImpl, and topImpl the scripts don't make it past tdImpl because of the error shown below:

ERROR: [Opt 31-65] LUT input is undriven either due to a missing connection from a design error, or a connection removed during opt_design. LUT cell name: aes_128_0/s0[95]_i_1

I find this same error explained here in UG904, where it says, "This error often occurs when the connection was omitted while assembling logic from multiple sources. Logic optimization identifies both the cell name and the pin, so that it can be traced back to its source definition."

 

I've noticed that when I run the topSynth, tdImpl, and topImpl portions of the HD flow, my *_ooc_optimize.xdc file is populated with 194 ports that are tied to logic zero. The error happens in the middle of the opt_design run of tdImpl. This leads me to believe that the opt_design run is causing the problem.

 

The aes_128_0/s0[95]_i_1 leaf cell, in the design should have two inputs: aes_128_0/state[95] and aes_128_0/key[95]. Neither of those wires end up in the *_ooc_optimize.xdc file during the course of the HD flow. 

 

Any ideas on why this is happening and what I can do to use this module in my top level design?

 

--Sean

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byusean
Observer
Observer
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Registered: ‎01-25-2017

woodsd,

 

Thank you so much for your response. It helped me to realize that I was kind of asking the wrong question. Part of my problem was, as you said, that one of the wires in my module was unplaced/unrouted because it had no driver. I was able to go into the ./Implement/TopDown/top_opt_design_error.dcp, find the LUT2 that wasn't being driven, and realize that that LUT was having a problem.

 

The larger problem was in my understanding of the Hierarchical Design flow and what each step in the process is supposed to take in, do, and output. At least this information will be here because I'm posting it, but I believe that the following information should be made clearer in UG905 and UG946.

 

Top Synth (topSynth)

Purpose: This will synthesize all of the HDL files referenced by your ./Sources/prj/top.prj file, including the interface to the OOC module provided by any files in ./Sources/hdl/blackbox/.

Input: Every file referenced by top.prj.

Output: ./Synth/top/top_synth.dcp and related log files.

 

OOC Synth (oocSynth)

Purpose: This will synthesize all of the HDL files referenced by your ./Sources/prj/{module}.prj file.

Input: Every file referenced by {module}.prj

Output: ./Synth/{module}/{module}_synth.dcp

 

Top Down Implementation (tdImpl)

Purpose: This will, based on the information Vivado has gleaned from Top Synth and the information contained in the top floorplan XDC file, let the OOC module know of optimizations/constraints by way of the {module} XDC files.

Input: ./Synth/top/top_synth.dcp, ./Sources/xdc/top_flpn.xdc

Output: ./Implement/TopDown/top_place_design.dcp

 

OOC Implementation (oocImpl)

Purpose: This will implement the OOC module based on the results from synthesis and the constraints that pertain to the {module} found in the ./Sources/xdc/ folder.

Input: ./Synth/{module}/{module}_synth.dcp, ./Sources/xdc/{module}_phys.xdc, ./Sources/xdc/{module}_ooc_timing.xdc, ./Sources/xdc/{module}_ooc_optimize.xdc, ./Sources/xdc/{module}_ooc_budget.xdc

Output: ./Implement/{module}/{module}_route_design.dcp (which then gets copied to ./Checkpoint/)

 

Top Implementation (topImpl)

Purpose: This is the final implementation of the FPGA design and the last stage in Hierarchical Design.

Input: ./Synth/top/top_synth.dcp, ./Sources/xdc/top.xdc, ./Checkpoint/{module}_route_design.dcp

Output: ./Implement/top/top_route_design.dcp

 

My goal was to create an OOC module that I could place in any design, kind of like a plug-and-play feature. My errors all came because I was running tdImpl and didn't actually understand what it was doing. Because tdImpl tries to optimize the entire design, passing optimizations from the top level to the OOC module, my OOC module kept on changing. What I needed was to skip tdImpl and just run the other four. I wanted an OOC module that was top-level agnostic, and tdImpl tied them together.

 

I believe that the error I mentioned above came because I would run oocSynth and oocImpl, and then topSynt, tdImpl, and topImpl. The router wouldn't find all of the nets it needed because they didn't exist.

 

I hope this helps someone!

 

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byusean
Observer
Observer
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Registered: ‎01-25-2017

Another aspect of this that I neglected to mention, but goes right along with this OOC module being changed by placing it in context is the following: when I implement the module by itself it has a certain number of leaf cells and nets but when I place it in context, it has a different number of leaf cells and nets.

aes_128_0_synth_impl.png

The picture above was taken from ./Implement/aes_128_0/aes_128_0_route_design.dcp. It shows 386 leaf cells, 3536 CLB/LUT's used, and 3968 REGISTER/SDR's used.

 

topDown_tdImpl.png

The picture above was taken from ./Implement/TopDown/top_opt_design_error.dcp. It shows 319 leaf cells, 3469 CLB/LUT's used, and 3901 REGISTER/SDR's used.

 

I do not want the ooc module to change after I synthesize and implement it. It should be the exact same in every design I use it in after that point.

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woodsd
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

Hi Sean,

 

The error you are seeing is simply stating that you have LUT with inputs that are not driven. It sounds like the leaf cell in the error is driven by two ports of the OOC module (key[95] and state[95]).  When tdImpl is run, it tries to identify any partition ports that are driven by constants (inputs) or that are unconnected (outputs), and create the "ooc_optimize.xdc" so that these ports can be correctly optimized during OOC implementation. In you top-level synthesized design, what is driving the aes_128_0/key[95] and aes_128_0/state[95] pins?  Typically synthesis will tie of any unconnected signals to constants. If these are driven by constants, they should have the appropriate "set_logic_*" constraint to allow optimization during the OOC implementation.  

 

Perhaps this design is a case that the tutorial scripts don't take into account, and you may need to modify these scripts (see the create_set_logic Tcl proc in hd_floorplan_utils.tcl). As an example, the proc is looking for a net with TYPE property of POWER or GROUND.  Perhaps the nets in this case are of a different type, but still one that should generate a set_logic_* constraint. Examining the post-link_design DCP in the tdImpl run should help you figure out how these ports are connected. Find the nets driving these pins, and determine why the proc didn't create a set_logic constraint for these.

 

It might be just as easy to modify the RTL for the top-level to make sure all of your partition ports are driven, and that you don't have any top-level logic being driven by outputs of the partition that are sourceless. 

 

Hope this helps.

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woodsd
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008
Review the HD tutorial and user guide. The TopDown flow is only intended to extract constraints (XDC) that drive the OOC implementation. Once OOC imlpementation is done, and the OOC module is being imported, it is only the topImpl that needs to be run. In this run the exact OOC implementation results will be used, and it will be locked. If you are starting with a synthesis DCP, the module will change based on the context it is being optimized in.

The tdImpl is a one time run unless there are changes to the floorplan or the partition interface.
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byusean
Observer
Observer
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Registered: ‎01-25-2017

woodsd,

 

Thank you so much for your response. It helped me to realize that I was kind of asking the wrong question. Part of my problem was, as you said, that one of the wires in my module was unplaced/unrouted because it had no driver. I was able to go into the ./Implement/TopDown/top_opt_design_error.dcp, find the LUT2 that wasn't being driven, and realize that that LUT was having a problem.

 

The larger problem was in my understanding of the Hierarchical Design flow and what each step in the process is supposed to take in, do, and output. At least this information will be here because I'm posting it, but I believe that the following information should be made clearer in UG905 and UG946.

 

Top Synth (topSynth)

Purpose: This will synthesize all of the HDL files referenced by your ./Sources/prj/top.prj file, including the interface to the OOC module provided by any files in ./Sources/hdl/blackbox/.

Input: Every file referenced by top.prj.

Output: ./Synth/top/top_synth.dcp and related log files.

 

OOC Synth (oocSynth)

Purpose: This will synthesize all of the HDL files referenced by your ./Sources/prj/{module}.prj file.

Input: Every file referenced by {module}.prj

Output: ./Synth/{module}/{module}_synth.dcp

 

Top Down Implementation (tdImpl)

Purpose: This will, based on the information Vivado has gleaned from Top Synth and the information contained in the top floorplan XDC file, let the OOC module know of optimizations/constraints by way of the {module} XDC files.

Input: ./Synth/top/top_synth.dcp, ./Sources/xdc/top_flpn.xdc

Output: ./Implement/TopDown/top_place_design.dcp

 

OOC Implementation (oocImpl)

Purpose: This will implement the OOC module based on the results from synthesis and the constraints that pertain to the {module} found in the ./Sources/xdc/ folder.

Input: ./Synth/{module}/{module}_synth.dcp, ./Sources/xdc/{module}_phys.xdc, ./Sources/xdc/{module}_ooc_timing.xdc, ./Sources/xdc/{module}_ooc_optimize.xdc, ./Sources/xdc/{module}_ooc_budget.xdc

Output: ./Implement/{module}/{module}_route_design.dcp (which then gets copied to ./Checkpoint/)

 

Top Implementation (topImpl)

Purpose: This is the final implementation of the FPGA design and the last stage in Hierarchical Design.

Input: ./Synth/top/top_synth.dcp, ./Sources/xdc/top.xdc, ./Checkpoint/{module}_route_design.dcp

Output: ./Implement/top/top_route_design.dcp

 

My goal was to create an OOC module that I could place in any design, kind of like a plug-and-play feature. My errors all came because I was running tdImpl and didn't actually understand what it was doing. Because tdImpl tries to optimize the entire design, passing optimizations from the top level to the OOC module, my OOC module kept on changing. What I needed was to skip tdImpl and just run the other four. I wanted an OOC module that was top-level agnostic, and tdImpl tied them together.

 

I believe that the error I mentioned above came because I would run oocSynth and oocImpl, and then topSynt, tdImpl, and topImpl. The router wouldn't find all of the nets it needed because they didn't exist.

 

I hope this helps someone!

 

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